Nokia Bell Labs


Wipe


PHOTONIC INTEGRATED CIRCUITS FEATURE


kits (PDKs) from European PIC and IC foundries. It will prototype a 400Gb/s transceiver for data centre applications. This includes an eight-channel transmitter that dissipates 2-3W of heat in the electronics and 2-3W in the photonic layer. Van Rijn’s simulations show this to be ‘challenging but doable’. ‘I’m focusing on thermal crosstalk between layers and reducing the temperature inside the laser cavity,’ he said. Meanwhile, IBM Research Zurich, in Switzerland, is designing the package and heat sinks.


Proceed with care The density of heat sources on PICs is generally also increasing, van Rijn noted, creating higher overall temperatures that lower efficiency and create greater thermal cross-talk. That includes lasers for wavelength division multiplexing, SOAs for lidar sensing, and thermal tuners for silicon devices. This mainly affects the structures with dense SOA arrays and, currently, the density is limited by thermal issues. ‘We could improve this situation by improving efficiency of the SOAs, using heat spreaders to lower the thermal resistance to ambient and by using aluminium-based SOAs since they can operate at higher temperatures,’ said van Rijn. WIPE’s use of thin InP membranes


reflects how the industry deals with differences in CTEs when integrating active components with silicon photonics. ‘For the III-V chip, it all has to do with how you affix it and connect it to the photonic chip,’ Barwicz said. ‘The smaller the


hybrid waveguide


encapsulant


heat sink


planarisation layer


InP photonic layer polymer bonding layer CMOS layer


metal interconnects Silicon


A cross-section for an integrated photonic/electronic chip, showing the silicon CMOS layer and the InP photonic layer, with the metal interconnect stack and the polymer bonding layer in between, and heat sink on top


III-V chip, the easier the CTE mismatch is to accommodate.’ To help manage CTE issues in a


different context, IBM has developed a polymer-based ‘compliant optical interface’ between standard optical fibres and silicon nanophotonic waveguides. ‘The compliant polymer interface helps with what is called chip-package interaction,’ Barwicz said. ‘The various CTEs of the various materials used in a package can create significant stresses within the package with environmental temperature cycling. This can lead to package failure with time. The soft connection of the polymer interface reduces those stresses and is expected to improve long-term reliability.’


μTEC


“Typically, the active optical devices, like lasers and semiconductor optical amplifiers, need to be maintained below 60°C, whereas silicon-based electronics are quite happy operating at 80-90°C”


IBM is commercialising this and its other silicon nanophotonic packaging solutions as a service at its Bromont, Canada, manufacturing site. One issue with using polymers to


Optical layer Thermal layer Electrical layer


manage thermal issues is that they can break down at high operating temperatures. However, IBM’s compliant optical interface is designed to take even higher manufacturing temperatures into account. ‘The polymer we use is very resistant to thermal degradation,’ Barwicz said. ‘It can withstand typical solder reflow at


Thermally Integrated Photonics System (TIPS) conceptual architecture. A stacked optoelectronic architecture composed of: an optical layer with waveguides, passive photonic components, active photonic components and device-integrated thermoelectric cooling; a thermal layer acting as an interposer that contains embedded microfluidics; and an electronic layer containing analogue and/or digital electronic functionality


www.electrooptics.com | @electrooptics


around 250˚C without measurable damage. Note typical upper temperature of service can be in the 80-85˚C range, so it is not that high.’ While Barwicz is confident about the capabilities of such technology to handle existing thermal issues, the future brings greater challenges. ‘Once we bring the photonics, and especially the laser, closer to the microelectronic logic chip generating the data, the heat from that microelectronics chip could heat the III-V in the photonic device and reduce the light output notably,’ he said. ‘This is especially true down the road, where people contemplate embedding such high-power microelectronic chips with photonics in one module. Careful thermal design will be required.’ EO


March 2018 Electro Optics 29


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