Feature: Edge AI
The sequential, one-instruction-
after-another model of computing that works so well for standard software is a poor fi t for AI software
a poor fit for AI software: AI models are formed as matrices, not as linear sequences, and call for massively parallel compute operations. Compiling a neural network’s MAC workload to the instruction set architecture (ISA) of a von Neumann-type processor generates huge numbers of operations; for a large language model (LLM) of between 50 billion and 500 billion parameters, a single inference can require from 100 billion to 1,000 billion operations. And, when performing billions of operations, an important determinant of a processor’s performance is memory access time, a well understood limitation of the von Neumann architecture. Even after optimising for performance by tying the fastest SRAM memory to the ALU, inference performance remains disappointing for the largest models, and also makes the processor very expensive. The memory access problem inherent
Figure 1: The classic von Neumann architecture handles sequential instructions effi ciently
in the fundamental compute block – the von Neumann unit – hamstrings parallel computing architectures such as a graphics processing unit (GPU) or neural processing unit (NPU) as much as it does a conventional CPU. Their speed and power consumption still depend on memory access: these digital architectures can’t get enough memory close enough to the ALU. They are limited by the slow speed of DRAM, which can’t be built on the same die as the ALU (a cause of performance/power problems with today’s GPUs), or by the limited capacity of fast on-chip SRAM.
Figure 2: A typical implementation of a systolic array
Fitting the compute architecture to the compute task The problems with implementing neural networking operations on conventional compute architectures has led computer scientists to explore a different approach – the systolic array (Figure 2) – which matches much better the interconnected, multi-layered structure of a neural network. However, previous attempts to implement a systolic array in silicon have struggled with the practical implementation of such a densely interconnected fabric. In addition, the physical separation of memory from
www.electronicsworld.co.uk February 2026 27
Page 1 |
Page 2 |
Page 3 |
Page 4 |
Page 5 |
Page 6 |
Page 7 |
Page 8 |
Page 9 |
Page 10 |
Page 11 |
Page 12 |
Page 13 |
Page 14 |
Page 15 |
Page 16 |
Page 17 |
Page 18 |
Page 19 |
Page 20 |
Page 21 |
Page 22 |
Page 23 |
Page 24 |
Page 25 |
Page 26 |
Page 27 |
Page 28 |
Page 29 |
Page 30 |
Page 31 |
Page 32 |
Page 33 |
Page 34 |
Page 35 |
Page 36 |
Page 37 |
Page 38 |
Page 39 |
Page 40 |
Page 41 |
Page 42 |
Page 43 |
Page 44 |
Page 45 |
Page 46 |
Page 47 |
Page 48
