Column: Silicon systems design
System-level verifi cation in the chiplet era
By Mike Bartley, CEO, Alpinum C
hiplet-based architectures are rapidly becoming a dominant approach for scaling performance, flexibility and cost efficiency in advanced
silicon systems. By decomposing large monolithic designs into smaller, reusable dies, engineers can mix process nodes, integrate heterogeneous IP and accelerate innovation across compute, memory and specialised accelerators. As chiplet adoption matures, however,
a critical challenge is becoming increasingly visible. Verification
complexity no longer resides primarily at the IP or die level. Instead, it emerges at the system level, where independently verified components interact in ways that are difficult to predict, observe and validate using traditional approaches. This shift has significant implications
for how verification is planned, executed and signed off. In chiplet- based systems, correct IP does not automatically result in correct silicon. Understanding why requires a closer examination of how integration complexity manifests in modern multi- die designs.
From IP verification to system behaviour For decades, verification practice has been organised around a clear hierarchy. Individual IP blocks are validated in isolation and then integrated at the SoC level, where additional checks focus on connectivity, coherence and top-level functionality. Once expected behaviours are demonstrated and regressions stabilise, designs progress toward tape-out. Chiplet-based systems challenge
this model. Each die may be developed by a different team, sourced from a different vendor, or optimised for a different process technology. While each component can be functionally correct within its own verification environment, system behaviour emerges only when these components interact. As the verification scope expands from
individual blocks to composed systems, assumptions that hold at the IP and SoC levels increasingly break down under system-level interaction.
Figure 1: Evolution of verifi cation scope from block-level validation to system-level behaviour as designs transition from monolithic SoCs to chiplet-based systems
12 February 2026
www.electronicsworld.co.uk
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