Feature: Edge AI
New type of compute architecture for Edge AI applications
By GP Singh, CEO and Founder, Ambient Scientific S
uch is the AI world’s hunger for compute capacity that the semiconductor industry struggles to keep up with the demand. OpenAI
CEO, Sam Altman, is perhaps the most prominent figure to go public about the shortage of AI chips. A TechCrunch report states that “in a Reddit AMA, OpenAI CEO, Sam Altman, admitted that a lack of compute capacity is one major factor preventing the company from shipping products as often as it would like”. The problem is not only compute
capacity: it is also the huge amount of electricity that AI data centres consume. These challenges experienced by
AI hyperscalers are mirrored in the miniature by manufacturers of edge products that perform on-device AI, often on battery power. Developers of edge applications want to use ever
larger AI and ML models, to benefit from more accurate inference and to inject more intelligence into the system. However, they are constrained by the slow AI performance and high power consumption of microcontrollers and microprocessors. Altman’s observation means that
the problem is not being solved fast enough by the semiconductor industry’s incremental approach to improving AI chips. Most semiconductor companies’ approach to AI is to use the conventional architecture of the compute function, and tweak it to make its execution of multiply-accumulate (MAC) operations that a neural network uses slightly faster and more efficient. Yet, general-purpose compute architecture is poorly suited to the massively parallel and connected matrix computing operations required by AI systems. The AI industry’s hunger for low- power, high-speed matrix computing
26 February 2026
www.electronicsworld.co.uk
needs a fundamental new approach at the silicon level, and some companies like Ambient Scientific, aim to address it.
Conventional von Neumann architecture: Inefficient in neural networks The classic von Neumann architecture has been the mainstay of general- purpose computing for decades; see Figure 1. This model, which operates by fetching, decoding and executing instructions sequentially in a cycle that involves a control unit, an arithmetic logic unit (ALU) and memory has dominated because it handles effectively the sequential instructions that underpin conventional software applications, and because the architecture is flexible, simple and relatively easy to fabricate in silicon. But the sequential, one-instruction-
after-another model of computing that works so well for standard software is
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