Column: Silicon systems design
with system workloads, and cross- domain correlation between RTL, firmware and emulation results. However, it is worth pointing
out that AI does not replace engineering judgment. Its value lies in augmenting visibility and prioritisation, not in making verification decisions autonomously. Explainability and traceability remain essential, especially in safety- and reliability-critical designs.
Architectural implications System-level verification cannot be retrofitted late in the design cycle – it must be considered during architecture definition, where decisions about partitioning, interfaces and observability have long-term consequences. Teams that plan for system-level
Conceptual illustration showing how functional coverage and scoreboard-based verification environments can reach closure without guaranteeing correct behaviour at the system level [Source: Aldec]
rather than interface compliance alone.
• Power- and thermal-aware analysis that captures dynamic effects across operating conditions.
• Workload-driven validation using realistic software and traffic patterns.
• Hierarchical observability that maintains visibility across dies without intrusive instrumentation. These techniques do not replace
established practices. Instead, they extend visibility into system interactions that would otherwise remain opaque.
Standards for system visibility Industry standards play a critical role in enabling system-level verification. Without common access and observability mechanisms, integration complexity quickly becomes unmanageable. IEEE 1838 provides structured test
access architectures for stacked and multi-die systems, enabling predictable
entry points for validation and debug. UCIe establishes interoperable
die-to-die communication, including support for metadata exchange that aids validation and monitoring. Open Compute Project (OCP)
initiatives define open frameworks for system-in-package testing and cross- vendor interoperability. Together, these standards create a
foundation for system-level verification that scales across suppliers and integration models.
Where AI supports verification Artificial intelligence (AI) is increasingly applied to verification workflows, particularly at the system level, where data volumes exceed the capacity of manual analysis. Effective applications include
clustering and classification of failure signatures across large regression sets, identification of coverage gaps correlated
14 February 2026
www.electronicsworld.co.uk
verification early benefit from reduced bring-up time, faster root- cause identification and greater confidence in integration sign- off. Conversely, architectures that prioritise performance or reuse without considering verification often incur hidden costs during integration and post-silicon debug.
Evolving verification Chiplet-based systems represent a fundamental shift in how silicon is designed and integrated. As architectures evolve, verification must evolve alongside them. The centre of gravity is moving away from isolated component correctness toward system-level behaviour and interaction. For engineers, this shift demands
renewed attention to observability, standards adoption and verification strategy. In the chiplet era, understanding where integration complexity truly emerges is essential to delivering reliable, scaleable silicon systems.
This column continues in next month’s edition of Electronics World.
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