XJTAG – Experts in JTAG / Boundary Scan
What is JTAG and how can I make use of it?
What is XJTAG’s advanced connection test?
A JTAG connection test will check that the connections around the JTAG enabled devices on a board are the same as those specified in the design.
Where two JTAG enabled pins are meant to be connected the test will make sure one pin can be controlled by the other. Where enabled pins are not meant to be connected they are tested for short circuit faults by driving one pin and checking that these values are not read on the other pins. Missing pull resistors and ‘stuck-at’ faults can also be found.
XJTAG’s advanced connection test also checks for other problems such as short circuit faults beyond series resistors as well as automatically testing for faults around devices whose behaviour can be described in a truth table.
What about devices that are not JTAG enabled?
While the main devices, such as processors and FPGAs, are normally JTAG enabled, there will be many devices in every design that are not. DDR, SDRAM, SRAM, flash, MDIO controlled Ethernet PHYs, SPI and I2C temperature sensors, real time clocks, ADCs and DACs are just some examples of such devices.
The connection test will still provide excellent coverage for short circuit faults on the nets linking these non-JTAG devices to JTAG enabled devices; however it cannot check for open circuit faults at either the JTAG device or the non-JTAG device.
In order to add this open circuit coverage it is necessary to communicate with the peripheral device from boundary scan on the enabled device. If communication can be verified, there cannot be an open circuit fault. This type of testing can be very simple, for example lighting an LED and asking an operator to verify it has activated, or more complex, for example writing data into the memory array of a RAM and reading it back.
Is it a lot of work to create an XJTAG test system?
Using the library for standard non-JTAG components installed with XJTAG software, you can get a set of tests up and running for your board with no code development. The XJTAG library contains models for all types of non-JTAG devices from simple resistors and buffers to complex memory devices such as DDR3. Because boundary scan disconnects the control of the pins on JTAG devices from their functionality the same model can be used irrespective of the JTAG device controlling a peripheral.
Most boards already contain JTAG headers for programming or debug so there are no extra design requirements. Where do I get information about the JTAG in my devices?
In order to run any boundary scan based testing it is necessary to have some information about the implementation of JTAG on the enabled devices on a board. This information comes from the BSDL (Boundary Scan Description Language) files for these devices. BSDL files must be made available by the silicon vendor for a device to be compliant with IEEE Std. 1149.1.
Is JTAG test just used in production?
Not at all. One of the key benefits to boundary scan testing is that the only test hardware required is a JTAG controller. Other production test technologies such as flying probe, automated optical/X-ray inspection or bed-of-nails all require specialised test equipment that will not be available on an engineer’s bench.
Using boundary scan during board bring-up can remove uncertainties – hardware engineers can test prototype boards for manufacturing defects before system testing, and even before firmware is complete. Test systems developed at this early stage of the product lifecycle can easily be reused, and extended for production.
+ 3.3v + 3.3v
Missing pull resistor Stuck at 1 OK
Short Short Resistive short Resistive short Open
Logic connection
Stuck at 0 Missing pull resistor
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