Test & Measurement


Improved DAC phase noise measurements enable ultralow phase noise DDS applications


In this article, Peter Delos, technical lead and Jarret Liner, RF systems application engineer, both in the aerospace and defence group at Analog Devices, show measured improvements of over 10 dB at 10 kHz offsets using the AD9164 DAC


I


n radar applications, phase noise is a critical performance metric for systems requiring high clutter attenuation. Phase noise is a concern for all radio systems, but radar in particular can require phase noise performance at frequency offsets much closer to the carrier than a communication system.


System designers in these high performance systems will choose ultralow phase noise oscillators and the objective of the signal chains, from a noise perspective, is to add minimal degradation to the oscillator phase noise profile. This requires residual or additive phase noise measurements of the varied components in the signal chain. Recent product releases of high speed digital-to-analog converters (DACs) are extremely attractive for both waveform generation and frequency creation for any LOs needed in frequency conversion stages. The radar objectives, however, challenge the DAC phase noise performance. This article shows measured


improvements of over 10 dB at 10 kHz offsets using the AD9164 DAC. Figure 1 illustrates the improvement and we will discuss how the results were achieved through a combination of both power supply regulator selection and test setup improvements.


Phase noise definition Phase noise is a measure of the deviation in the zero crossing of a periodic signal. Consider a cosine wave with phase fluctuations


Figure 2: Absolute phase noise DDS test setup includes both DAC and oscillator noise


Phase noise is determined from the power spectral density of the phase variations


single DDS is required. However, with this test setup there is no method to extract the oscillator contribution to show only the DDS phase noise. Figure 3 shows two common methods to remove the oscillator phase noise from the measurement, providing a residual noise measurement. The drawback of the measurements is that additional DACs are required in the test setup. However, the benefit is a much better indicator of the DAC phase noise contribution that can be applied in system-level analysis budgets.


In linear terms, the single sided phase noise is defined as


Phase noise is normally expressed in units of dBc/Hz from 10log(L(f)). Phase noise data is then plotted at offset frequencies relative to the RF carrier. An important further definition of phase noise is absolute phase noise vs. residual phase noise. Absolute phase noise is the total phase noise measured in the system. Residual phase noise is the additive phase noise of the device under test. This distinction becomes critical in the test setups and in the process of determining component level phase noise contributions in a system.


DAC/DDS phase noise measurement methods The figures in this section illustrate DDS phase noise test setups. For DAC phase noise measurements, it is assumed the DAC is used as part of a direct digital synthesizer (DDS) subsystem. A DDS is implemented with a digital sinewave pattern to a DAC that could be in a monolithic IC or an FPGA or ASIC


Figure 1: AD9164 phase noise improvements 44 October 2017 Components in Electronics


communicating to a DAC. In modern DDS design, the digital phase errors can be made much less than the DAC errors, and DDS phase noise measurements are typically limited by the DAC performance. The simplest and most common test setup is shown in Figure 2. A clock source is used for the DDS and the DDS output is fed to a cross correlation type phase noise analyser. This is easy to implement since only a


Figure 3a: DDS residual phase noise measurement using the phase detector method


Measured results During investigation of the true DAC phase noise performance, both the test setups and the regulator noise performance were considered.


The initial DAC evaluation


board included the ADP7140 regulator for the analog and clock voltages. Noise spectral densities were compared with recently released ultralow noise regulators and the ADM7155 was chosen. Next, test setup options


Figure 3b: DDS residual phase noise measurement using the cross correlation method


were considered for residual phase noise measurements. The cross correlation method was chosen with the Rohde and Schwarz FSWP primarily out of availability and convenience. The measurement in


figure 4 indicates three general regions of limitations in the initial measurement that were not obvious in the beginning of the investigation. Frequencies below 1 kHz were limited by the close in noise of the clock source. Frequencies from 1 kHz to 100 kHz were limited by the regulator selection. Frequencies above 100 kHz were limited by the clock source. The sharp drop off above 10 MHz is the clock source contribution as the clock used was a multiplied crystal oscillator to create 6 GHz and the roll-off is from the RF filters used in the multiplication stages.


Figure 4: AD9164 800 MHz output phase noise comparisons www.analog.com www.cieonline.co.uk


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