Supplement: Power
Optimize clock performance in the presence of power supply noise
By Jehangir (JP) Parvereshi, technical director, customer engineering at SiTime
PCB layout of a differential oscillator including the power supply rail connection and associated bypass capacitors (left); Simulated power supply waveform illustrates the impact of improper use of a bypass capacitor. With no bypass capacitor the power supply noise is 90 mV peak to peak versus 20 mV peak-to-peak ripple with a bypass capacitor placed very close to the oscillator VDD pins (bottom).
P
ower supply noise poses a significant challenge to electronic system design. To optimize system performance, engineers must ensure that
clocks are resilient to power supply noise. This noise can couple through a clock or timing device to appear as jitter on an output clock.
These two practical strategies can mitigate the effects of power supply noise to maintain optimal system clock performance.
Two methods for power supply noise reduction
1. Add sufficient bypass capacitors to power pins.
In the following example, a differential oscillator clocks a high-speed 100 GbE PHY, but the oscillator exhibits higher- than-expected phase-noise spurs in the 100 kHz to 1 MHz range. This is caused by excessive noise on the reference clock’s power (VDD) pin.
The simulated power supply waveform (top right) demonstrates the impact of improper use of a bypass capacitor. With no bypass capacitor the supply noise is 90
32 July/August 2025 AC frequency response simulation of a problematic LC filter showing resonance peaking.
mV peak to peak. Placing a low Equivalent Series Resistance (ESR) capacitor (0.1µF–1µF) near the VDD pin minimizes high-frequency noise. In this case, power supply noise was reduced from 90 mV peak to peak to 20 mV peak-to-peak ripple. This illustrates the importance of using low
Simulation of a problematic LC filter: Transient response. Components in Electronics
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