Feature sponsored by
Test & measurement Performing high speed testing and DC
Richard Houlihan, product marketing manager
parametric testing using relays becomes challenging as most relays do not operate beyond 8GHz, so users have to compromise on signal speed and test coverage. Moreover, relays are big in size and consume a large PCB area, which impacts the solution size. Reliability is always a concern for relays as they typically only last for 10 million switching cycles, which limits system uptime and load board lifetime. Figure 3 shows a two insertion test method to
Naveen Dhull, product applications engineer
perform a high speed loopback test and a DC parametric test. In Figure 3, the left side shows the high speed digital loopback test setup, where the transmitter of the DUT is connected back to the receiver through a coupling capacitor. On the right side of Figure 3 is the DC parametric test setup where DUT pins are directly connected to the ATE tester for parametric tests. Until now, it has not been possible to have both high speed loopback and DC test functionality on the same load board due to component limitations.
CHALLENGES ASSOCIATED WITH TWO TEST INSERTIONS
Management of two sets of hardware: Users must maintain and manage two sets of load boards required for DC and loopback test. This adds significant overhead, particularly when testing a high volume of parts.
Padraig Fitzgerald, principal IC design engineer
Figure 1. Operator mounting load board on tester for testing digital SoC.
HOW ARE HSIO PINS TESTED? Testing high speed input output (HSIO) interfaces in a high volume manufacturing environment is a challenge. A common approach to validate an HSIO interface is to implement a high speed loopback test architecture. This incorporates both high speed and DC test paths in one configuration. To perform high speed loopback testing,
generally a pseudorandom bit sequence (PRBS) is transmitted at high speed from the transmitter and received at the receiver end after being looped back on the load board or test board as shown in Figure 3 (left side). At the receiver end, the sequence is analysed to calculate the bit error rate (BER). DC parametric tests, such as continuity and
leakage tests, are performed on I/O pins to ensure device functionality. To perform these tests, pins need to be connected directly to a DC instrument where a current is forced and a voltage is measured in order to test for failures. To perform both a high speed loopback test
and a DC parametric test on the DUT I/Os, there are a few methods that can be used to test the digital SoC; for example, using MEMS switches or relays, or using two different types of load boards, one for high speed testing and the other for DC testing, which requires two insertions.
Instrumentation Monthly January 2023
Higher test time and higher test cost: Two test insertion means every DUT must be tested twice, hence the indexing time during each test will be doubled, which ultimately increases the test cost and impacts the test throughput significantly.
Test time optimisation: Test times cannot be optimised when two sets of hardware are involved. More cost will be incurred if a part fails the second insertion. The first insertion will have been wasted tester time.
More prone to human error: Since every DUT is tested twice, it doubles the risk of human error.
Solution set up x 2: The two test insertion approach involves two sets of hardware, which doubles the hardware setup time.
Logistics overhead: The two test insertion requires more component moves. It requires moving the components between testers and potentially between test houses, creating planning and logistical challenges.
HOW ADI’S DC TO 34GHZ SWITCH TECH SOLVES THE DOUBLE INSERTION PROBLEM WITH SUPERIOR DENSITY ADI’s 34GHz MEMS switch technology offers both high speed digital and DC testing capability with superior density in a small 5mm x 4mm x 0.9mm LGA package, as shown in Figure 4. To perform a high speed digital test, high speed signals from a transmitter are passed through the
Figure 3. Illustration of a two insertion test methodology.
switch and routed back to a receiver, where after decoding, the BER is analysed. For parametric DC testing, the switch connects the pins to the DC ATE tester where parametric tests such as continuity and leakage tests are performed to ensure device functionality. During parametric DC testing, MEMS switches also provide an option to communicate with ATE at high frequency, which is required in some applications. Figure 5 shows a high speed digital testing
solution comparing the use of relays and ADGM1001 MEMS switches. The solution provided by the MEMS switches is nearly 50 per cent smaller than the relay solution as the ADGM1001 comes in a 5 x 4 x 0.9mm LGA package, which is 20x smaller than a typical relay. The high frequency standards such as PCIe Gen 4/5, PAM4, USB 4, and SerDes drive multiple transmitter and receiver channels, which require intense PCB densification without any layout complication to mitigate channel-to-channel variation. To meet the demand of these evolving high frequency standards, MEMS switches offer intense densification and enhanced functionality in the load board design for digital SoC testing. Relays are typically large and have limited
high frequency performance. They struggle to support higher frequency standards such as PCIe Gen 4/5, PAM4, USB 4, and SerDes with enhanced densification. The majority of the relays do not operate beyond 8GHz and their poor insertion loss at high frequencies impacts the signal integrity and limits the test coverage.
AN INTRODUCTION TO ADGM1001 The ADGM1001 SPDT MEMS switch provides class-leading performance from DC to 34GHz. Due to the ultralow parasitics and wide bandwidth of the technology, the switch has minimal impact on signals up to 64Gbps and
Figure 4. ADGM1001 enabling both high speed
digital and DC testing (highlighting P channel only). Continued on page 34... 35
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