Test & measurement
AccelerAte Your test cApAbilitY And sYstem productivitY with new mems switches
By Richard Houlihan, product marketing manager, Naveen Dhull, product applications engineer, and Padraig Fitzgerald, principal IC design engineer, all at Analog Devices
Advanced digital processor ICs require separate DC parametric and high speed digital automatic test equipment (ATE) passes for quality assurance. This creates significant cost and logistical challenges. This article explains how the ADGM1001 SPDT MEMS switch facilitates a one pass single insertion test for both DC parametric and high speed digital tests, reducing test cost and simplifying logistics for digital/RF system on chip (SoC) testing.
34 T
he semiconductor market is evolving with higher speed and higher density interchip communications for advanced processors such as 5G modem ICs, graphics ICs, and central
processing ICs. Assuring quality amidst this increasing complexity and demand for increased throughput is the ultimate challenge for today’s ATE designers. One critical aspect is the increasing number of transmitter (Tx)/receiver (Rx) channels, which require both high speed digital and DC parametric testing. These challenges are driving complexity in semiconductor tests and not addressing them leads to increased test time, increased load board complexity, and reduction in test throughput. In turn, this will drive up operational expenses (OPEX) and reduce productivity in a modern ATE environment. To solve these ATE
challenges, a switch that is
operational at DC and high frequencies is needed. ADGM1001 can pass true 0Hz DC signals and up to 64Gbps high speed signals. This enables an efficient single test platform (one insertion) that can be configured to test both DC parameters and high speed digital communication standards, such as PCIe Gen 4/5/6, PAM4, and USB 4.
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Figure 2. ADGM1001 eye diagram at 32Gbps (RF1 to RFC with reference trace, pattern used PRBS 215-1
). January 2023 Instrumentation Monthly
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