Signal conditioning
HOW TO OPTIMISE A SECOND-ORDER OUTPUT FILTER FOR AN ULTRALOW NOISE µMODULE REGULATOR
By George (Zhijun) Qian, Senior Analog Design Engineering Manager, and Jennifer Florence Joseph Benedicto, Senior Design Evaluation Engineer, Analog Devices
Question:
Can we further reduce the
output switching noise of an ultralow noise µModule regulator?
Answer:
The output noise of an ultralow noise µModule regulator can be reduced by over 90 per cent using a second-order output filter. Proper care must be taken to select the capacitor and inductor components to maintain fast and stable control loop. This design is particularly beneficial for wireless and RF applications, where a fast transient response minimises system blanking time and maximises signal processing efficiency. This methodology achieves noise levels comparable to an LDO with the efficiency of a switching regulator.
P 60
ower consumption for noise sensitive devices is increasingly growing. Applications such as medical ultrasound imaging systems, 5G transceivers, and automatic test equipment (ATE) demand high output current (>5A) with a low noise level and high bandwidth in a small PCB area. Due to the high output current demand, the traditional two stage (buck + low dropout (LDO) regulator) solution that was previously used requires more PCB area and incurs more power loss, making it less preferred.
The LTM4702 ultralow noise µModule regulator features Analog Devices’ proprietary Silent Switcher technology, an ultrafast transient response, and ultralow noise architecture. All these features make it ideal for high current and noise-sensitive applications, while still maintaining the high efficiency of a synchronous switching regulator. This solution could eliminate LDO circuitry for many applications, which saves LDO cost (~60 per cent), LDO power loss (4W and
up), and LDO PCB space (2cm2 + clearance).
For certain applications requiring a very small switching frequency ripple, it is well known that a second-order LC filter can reduce the switching frequency harmonics of the output voltage. However, the design challenge is minimising the switching ripple while still maintaining a stable control loop with high control loop bandwidth. Often, the control loop becomes unstable after adding an un-optimised LC filter, which causes
the output to oscillate. In this article, a simplified loop analysis of the second-order LC filter is first discussed, and then an intuitive design method is given to guide on capacitance distribution and inductance calculation. Lastly, the LTM4702 design example verifies the proposed design method.
LOOP ANALYSIS OF A SECOND-ORDER LC OUTPUT FILTER DESIGN
In a current-mode buck regulator, the output
Figure 1. A current-mode buck regulator along with a second-order LC and its typical Bode plot. August 2026 Instrumentation Monthly
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