Data acquisition


Figure 9. ADN4654 jitter specification.


Quantifying the aDC’s aperture Jitter Aper ture jitter is inherent within the ADC. It is due to the sample-to-sample variation in aper ture delay, which corresponds to an error voltage in the sampling event. This sample-to-sample variation in the instant the switch opens is called aper ture uncer tainty, or aper ture jitter, and usually measured in rms picoseconds. In an ADC, as shown in Figure 10 and 11,


the aperture delay time is referenced to the input of the converter ; the effects of the analogue propagation delay through the input


buffer, ta; and the digital delay through the switch driver, tdd. Referenced to the ADC inputs, aperture time, ta’, is defined as the time difference between the analogue propagation


delay of the front-end buffer, tda, and the switch driver digital delay, tdd, plus one-half the aperture time, ta/2. In the case of the ADAQ23875, the


aperture jitter is only around 0.25 psRMS as shown in Figure 12. This specification is


guaranteed by design and not subject to test.


Overall sampling ClOCk Jitter After quantifying the individual jitter contribution of the four major blocks shown in Figure 3, the overall jitter performance of the signal (or clock) controlling the S&H switch can be calculated by taking the root sum of squares (RSS) of the four jitter sources.


On the other hand, if STA was used, the simplified clock jitter equation would be:


Figure 13. The effects of sampling clock jitter. ΔVrms = the rms voltage error and Δt = the


rms aperture jitter tj, and substitute these values:


And solving for ΔVrms: The rms value of the full-scale input sine wave is Figure 10. ADC’s sample-and-hold input stage.


effeCts Of sampling ClOCk Jitter On snr Having quantified the overall jitter on the signal controlling the S&H switch, we can now quantify how much that jitter will impact the SNR performance of the DAQ signal chain. Figure 13 illustrates the error due to jitter


on the sampling clock. The effects of sampling clock jitter on an


ideal ADC’s SNR can be predicted by the following simple analysis. Assume an input signal given by:


Figure 11. Sample-and-hold waveforms and definitions.


dividing the amplitude, 2πfVO, by √2. Now let


The rate of change of this signal is given by: The rms value of dv/dt can be obtained by


VO/√2. Therefore, the rms signal to rms noise ratio (expressed in dB) is given by frequencies:


This equation assumes an infinite resolution


ADC where aperture jitter is the only factor in determining the SNR. This equation is plotted in Figure 14 and shows the serious effects of aperture and sampling clock jitter on SNR and ENOB, especially at higher input/output.


Figure 12. ADAQ23875 aperture jitter. Instrumentation Monthly March 2022


Figure 14. Theoretical data converter SNR and ENOB due to jitter vs. full-scale sine wave input frequency.


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