Data acquisition
visualised by an offset crossover such that at 0 V, the two edges are separated (easily seen by the separation in the histogram in Figure 7). DDJ arises from a difference in propagation delay across operating frequency, while ISI is due to the influence of previous transition frequencies on the current transition (for example, edge timing will typically be different after a train of 1s or 0s vs. a 1010 pattern). Figure 8 shows how to fully estimate the
Figure 5. A static timing analysis (STA) example view.
data sheet defines the phase noise performance, it can be converted to jitter.
Quantifying the Jitter from the fPga The main role of the reference clock in an FPGA is to provide a trigger signal to start different parallel events programmed inside the FPGA. In other words, the reference clock orchestrates all the events inside the FPGA. To provide a better time resolution of the timing, the reference clock is usually passed to a PLL inside the FPGA to increase its frequency - thus, small time interval events will be possible. It is also important to know that there is a trigger- to-execution path inside the FPGA where the reference clock is passed to clock buffers, counters, logic gates, etc. When handling jitter sensitive repetitious events - such as providing an LVDS convert-start signal to an ADC via isolation - it is important to quantify the jitter contribution from the FPGA to properly estimate the impact on the overall system jitter to the high speed data acquisition performance. The jitter performance of the FPGA is
usually defined on the FPGA data sheet. It can also be found in the static timing analysis (STA) of most FPGA software tools, as shown in Figure 5. The timing analysis tool can calculate the clock uncertainty from the source and destination of a datapath and combine them together to form the total clock uncertainty. In order to automatically compute the contribution of the reference clock jitter in the STA, it must be added as Input Jitter Constraint in the FPGA project.
Quantifying the Jitter from Digital isolation The most basic method of viewing jitter is to measure an LVDS signal pair with a differential probe and trigger on both rising and falling edges, with the oscilloscope set to infinite persistence. This means that high-to-low and low-to-high transitions are superimposed, allowing measurement of the crossover point.
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The width of the crossover corresponds to the peak-to-peak jitter or time interval error (TIE) measured so far. Compare the eye diagram and histogram shown in Figure 6 and Figure 7. Some jitter is due to random sources (for example, thermal noise), and this random jitter (RJ) means that the peak-to-peak jitter seen on the oscilloscope is limited by the run time (the tails on the histogram will grow as the run time increases). By contrast, sources of deterministic jitter
(DJ) are bounded, such as jitter due to pulse skew, data dependent jitter (DDJ), and intersymbol interference (ISI). Pulse skew arises due to a difference between high-to-low and low-to-high propagation delays. This is
Figure 8. Total jitter contribution. RJ is specified as a 1 sigma rms value from Figure 6. Eye diagram for ADN4651.
the modeled Gaussian distribution, meaning that to extrapolate to longer run lengths (low BERs), one simply chooses the appropriate multiple sigma to move far enough along the tails of the distribution (for example, 14 sigma for 1 × 10-12 bit errors). DJ is then added to provide the TJ@BER estimate. For multiple elements in a signal chain - rather than adding multiple TJ values, which will overestimate jitter- RJ values can be geometrically summed and DJ values algebraically summed, allowing a more reasonably complete TJ@BER estimate for a complete signal chain. RJ, DJ, and TJ@BER are all specified
separately for the ADN4654, with maximums provided for each based on statistical analysis of multiple units to guarantee these jitter values across power supply, temperature, and process. Figure 9 illustrates an example of the jitter
Figure 7. Eye diagram histogram for ADN4651.
specification for the ADN4654 LVDS isolator. In the case of an isolated DAQ signal chain, additive phase jitter is the most important jitter specification. The additive phase jitter, together with other jitter sources, adds to the ADC’s aperture jitter that causes sample time imprecision.
March 2022 Instrumentation Monthly
total jitter for a given bit error rate (TJ@BER). RJ and DJ can be calculated based on model- fitting to a TIE distribution from measurement. One such model is the dual-Dirac model, which assumes a Gaussian random distribution convolved with a dual-Dirac delta function (the separation between the two Dirac delta functions corresponding to the DJ). For TIE distributions with significant deterministic jitter, the distribution will visually approximate this model. One complication is that some DJ can contribute to the Gaussian component, meaning that the dual-Dirac model can underestimate DJ and overestimate RJ. However, the two combined will still allow an accurate estimate of the total jitter for a given BER.
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