Data acquisition
The easy steps to calculate sampling clock jitter for isolated, precision high speed DAQs
By Lloben Paculanan, staff applications development engineer at Analog Devices and John Neeko Garlitos, product applications engineer at Analog Devices
eliminate ground loops that can introduce an error into a measurement. ADI’s precision, high speed technology enables system designers to achieve high AC and DC accuracy with the same design, without having to trade off DC accuracy for higher sampling rates. However, to achieve high AC performance, such as signal-to- noise ratio (SNR), the system designer needs to take into account the error introduced by jitter on the sampling clock signal or convert- start signal that controls the sample-and-hold (S&H) switch in the ADC. Jitter on the signal controlling the S&H switch becomes a more dominant error as the signal of interest and sample rates increase. When the DAQ signal chain is isolated, the
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signal for controlling the S&H switch typically comes from the backplane for multichannel, synchronised sampling. It is crucial that a system designer selects a digital isolator that has low jitter so that the resultant control signal going to the ADC’s S&H switch has low jitter. LVDS is the preferred interface format for precision, high speed ADCs because of the high data rate requirements. It also creates minimal disturbance on the DAQ power and ground planes. This article will explain how to interpret the jitter specifications on Analog Devices’ LVDS digital isolators and which specifications are important when interfacing to precision, high speed products such as the ADAQ23875 DAQ µModule solution. The guidance outlined in this article is applicable when using other precision, high speed ADCs with an LVDS interface. The approach for calculating the expected impact on the SNR will also be explained in the context of the ADAQ23875 when used in conjunction with the ADN4654 gigabit LVDS isolator.
How Jitter imPActs tHe sAmPLiNG Process Typically, a clock source has jitter in the time domain. Understanding how much jitter the clock source has is important when designing a DAQ system. Figure 1 shows the typical output frequency
spectrum of a nonideal oscillator with the noise power in a 1 Hz bandwidth as a function of frequency. Phase noise is defined as the ratio of the noise in a 1 Hz bandwidth at a specified
frequency offset, fm, to the oscillator signal amplitude at the fundamental frequency, fo.
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any data acquisition (DAQ) applications require an isolated DAQ signal chain path for robustness, safety, high common-mode voltage, or to
Figure 1. Oscillator power spectrum due to phase noise.
The sampling process is a multiplication of
the sampling clock and the analogue input signal. This multiplication in the time domain is equivalent to convolution in the frequency domain. Therefore, during ADC conversion, the spectrum of the ADC sampling clock is convolved with the pure sine wave input signal, and, thus, jitter on the sampling clock or phase noise will appear in the FFT spectrum of the ADC output data, as shown in Figure 2.
a certain voltage offset. Enabling the DAQ signal chain to track the common-mode voltage associated with the sensor eliminates the need for the input signal conditioning circuitry to accommodate large input common-mode voltages and remove that high common-mode voltage for the downstream circuitry. The isolation also provides safety to the user and removes ground loops, which can impact the measurement accuracy. Synchronising the sampling event across all
DAQ channels is crucial in a power analyser application because mismatch in the time domain information associated with the sampled voltage will impact the follow-on calculations and analysis. To synchronise the sampling event across channels, the ADC sampling clock comes from the backplane through the LVDS isolator. In the isolated DAQ architecture shown in
Figure 3, the following jitter error sources contribute to the total jitter on the sampling clock controlling the S&H switch in the ADC.
Figure 2. The effect of sampling an ideal sine wave with a phase noise sampling clock.
isoLAteD PrecisioN, HiGH sPeeD DAQ APPLicAtioN An example of an isolated precision, high speed DAQ application is a multiphase power analyser. Figure 3 illustrates the typical system architecture with channel-to-channel isolation, and a common backplane for communication with a system compute or controller module. In this example we selected the ADAQ23875 precision, high speed DAQ solution due to its small solution footprint - making it easy to fit multiple isolated DAQ channels in a small form factor, thus reducing the weight of a mobile instrument for field testing use cases. The DAQ channel is isolated from the main chassis backplane by an LVDS gigabit isolator (ADN4654). Isolating each of the DAQ channels enables
each channel to be connected directly to sensors with significantly different common- mode voltages without damaging the input circuitry. The ground of each isolated DAQ channel tracks the common-mode voltage with
1. reference clock Jitter The first source of sampling clock jitter is the reference clock. This reference clock passes through the backplane to connect to each isolated precision, high speed DAQ module and other measurement modules plugged into the backplane. It serves as a timing reference for the FPGA; thus, the timing accuracy of all the events, digital blocks, PLL, etc. inside the FPGA are dependent on the reference clock’s accuracy. In some applications without a backplane, an on-board clock oscillator is used as a reference clock.
2. FPGA Jitter The second source of sampling clock jitter is the jitter added by the FPGA. It is important to remember that there is a trigger-to-execution path inside the FPGA, and the jitter specification of the PLL and other digital blocks inside the FPGA contribute to the overall jitter performance of the system.
3. LVDs isolator Jitter The third source of sampling clock jitter is the LVDS isolator. LVDS isolators have additive phase jitter that contributes to the overall jitter performance of the system.
4. ADc’s Aperture Jitter The fourth source of sampling clock jitter is the ADC’s aperture jitter. This is inherent to the ADC and defined on the data sheet.
March 2022 Instrumentation Monthly
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