IC packaging technology retrospective—part 4
One of the challenges for CSP devices
is providing strain relief in the package
to decouple the chip from the substrate
to which it was mounted in a manner
that had come to be expected with earlier
generation packages. The problem is that
there is a significant difference in CTE of
the silicon chip and the substrate to which
it was mounted, which could be as much as
a factor of 6X. For very small die with few
I/O, packaging engineers have determined
that leadframe packages without leads can
perform reliably for a range of applications.
For example, Amkor’s micro lead frame
(MLF) package, a member of the quad
flat pack-no lead (QFN) or small outline,
!
no lead (SON) family, has proven quite
popular. The accompanying figure provides
examples of peripheral and area array
CSPs. CSP technology continues to evolve
and grow. As mentioned earlier, a recently
released CSP package from Tessera actually
has miniature pins rather than solder balls
for contacts and the chain of innovation
continues.
This retrospective will continue next
month with a look back at the origins of
!
wafer level packaging.
Figure 1. Examples of chip scale packages, an area array package (FPBGA) is shown on the left (courtesy Tes-

sera) and a peripherally leaded QFN package on the right (courtesy AMKOR).
Verdant Electronics founder and president
Joseph (Joe) Fjelstad has more than 35 years of
Fjelstad is also a well known author writing on He was also formerly with Tessera Technologies,
international experience in electronic intercon-
the subject of electronic interconnection technol- a global leader in chip-scale packaging, where he
nection and packaging technology in a variety
ogies. Prior to founding Verdant, Mr. Fjelstad was appointed to the first corporate fellowship
of capacities from chemist to process engineer
co-founded SiliconPipe a leader in the develop- for his innovations.
and from international consultant to CEO. Mr.
ment of high speed interconnection technologies.
2009 Global SMT & Packaging Reader Rework Survey
In the first quarter of this year, Global • Incorrectly
SMT & Packaging surveyed readers on programmed parts or
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their rework activities and rework systems. parts that were not
:+-.4&<&-)*'+,$+-(-.#*
Here is a sampling of what we learned from programmed prior to
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the nearly 500 respondents: installation
898*:+--('.+4#*
What users are looking for
6))*7+4,*'+,$+-(-.#*
Top three most important features in a
in future rework systems:
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rework system:
• More preheat
34+-2*$+%&4".5*
• BGA/QFP handling
capability
1&,&2()*'+,$+-(-.#*
• Profiling capability
• Faster heating/
/"0()*%(&)#*
• Tip selection
ramp up
!"#$%&'()*'+,$+-(-.#*
Some of the uses for rework systems, be- • Easier and better
yond our list of commonly rework defects, profiling
participate, email tgalbraith@globalsmt.net. A
that our readers listed: • Greater selection of nozzles or tips,
drawing will be held after the survey closes,
• Insufficient solder or universal tips
and one lucky respondent will receive a
• Testing new parts versions or • Capability for QFN/LGA/BGA/
brand new iPod Touch.
removal for failure analysis WL-CSP/01005/PoP
• Need to make additional compo- • Traceability
(Advertisers are eligible to contribue questions to
nent changes or swap out com- • Built-in inspection, x-ray
surveys and benefit from the full results. Contact
ponents at customer request not
your local rep for more information.)
Next up: our pick & place survey. To
necessarily due to defects
6 – Global SMT & Packaging – June 2009 www.globalsmt.net
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