Feature: Embedded design


with the same stimulus and asynchronous events. The comparison is performed on each instruction retire and external event, to detect any discrepancy at the point of failure. In addition, running the simulations in the same SystemVerilog environment allows interactive debug, to uncover the discrepancy and review its root cause. Given the time and effort required


for the verification tasks, the usability and operational requirements are key factors in selecting the test plan’s methodology. Debug is one of the most underappreciated aspects of verification; while coverage analysis is the ultimate measure of completeness, most of the time and effort revolve around the detailed work of analysis and resolution.


Reference models for verification quality To successfully test a processor, three items are required: the RTL of the new processor implementation, test programs and a reference model. Processor reference models, also known as ISS (Instruction Set Simulators), are typically used in software development; however, for comprehensive design verification, a true reference model is also required. The requirements for a RISC-V processor reference model include: • Model the full RISC-V ISA, including all versions of the ratified specification and stable unratified extensions;


• Configurability to select RISC-V ISA extensions;


• Customisation (e.g., instructions, CSRs);


• Ability to run in a co-simulation configuration;


• Can be controlled by another simulator; • Ability to “step” reference model at significant events (retire, trap);


• Can run in lock-step with the RTL simulator;


• Provides functions to query state of model, for comparison;


• Interface to software commercial and debug tools, e.g., GDB/Eclipse;


• Interface to software analysis tools, including access to processor internal state, etc.


20 May 2023 www.electronicsworld.co.uk Figure 3: RISC-V processor functional verification with ImperasDV and RVVI Most RISC-V ISSs can meet one or two


of these requirements, but it is essential that all of them are available for it to be considered as a RISC-V verification reference model. The established RISC-V reference model from Imperas meets all of these requirements; see Figure 3.


Freely available resources One popular, free ISS (Instruction Set Simulator) is riscvOVPsimPlus – an envelope model that can be configured to cover all of the ratified RISC-V specifications and standard extensions. Also included are several architectural validation test suites, which form a basic test plan for software-level compatibility within the specification definitions. RiscvOVPsimPlus includes a


proprietary freeware license that covers free commercial and academic use. The simulator package also includes a complete open-source model under the Apache 2.0 license. The free riscvOVPsimPlus package, including the Imperas RISC-V reference model, latest test suites with over 9.2 million instructions, and instruction coverage analysis, including updates for the latest RISC-V ratified specifications, is available on OVPworld; see box, right.


A new wave of innovation Te open-standard RISC-V specification is driving a new wave of innovation for processor designs for the next generation of domain-specific devices. However, every development team that explores the flexibility of RISC-V will also need to address the complexities of RISC-V verification. With the growing adoption of RISC-V,


a standards-based methodology for verification offers many advantages, including efficiency and reusability. Te flexibility of RISC-V offers developers freedom in design exploration, and the RISC-V Verification Interface (RVVI) complements this with a structured framework for verification.


RESOURCES:


• An open standard for the RISC-V Verification Interface (RVVI) is available on GitHub at https://github.com/riscv-verification/RVVI


• The free riscvOVPsimPlus package, including the Imperas RISC-V reference model, latest test suites with over 9.2 million instructions, and instruction coverage analysis, including updates for the latest RISC-V-ratified specifications, is available on OVPworld: www.ovpworld.org/riscvOVPsimPlus


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