Feature: RF Design
key components already in the pipeline. Filtronic, for instance, has initiated the design of a GaAs chipset specifically for this band, with expectations of releasing devices in the coming weeks. Manufacturing processes for the W-band are still compatible with existing methods, albeit pushing the boundaries of current manufacturing tolerances. This alignment allows for a smoother transition into higher frequency operations without necessitating a complete overhaul of established manufacturing infrastructures, thus accelerating the time-to-market for new technologies in this band. On the other hand, the progression
into the D-band presents a more complex scenario. Research in this area is advancing well, with available semiconductor processes in Indium Phosphide (InP) delivering the necessary power for high-frequency operations, though currently reliant on costly boutique processes. Te cost factor remains a critical hurdle that needs addressing to enable full commercial deployment. Moreover, integration challenges are more pronounced in the D-band; traditional wire bonds are unfeasible at these frequencies, necessitating the adoption of alternative interconnect technologies such as flip- chip, waveguide interfaces or hot vias. Tese technologies are essential
not only for performance but also for their potential scalability in volume manufacturing, a crucial factor for the commercial viability of telecommunications infrastructure in the D-band. As the industry navigates these challenges, the emphasis remains on innovation and precision engineering to harness the full potential of these higher frequency bands. While significant progress in the W
and D bands outlines promising short- term and mid-term advancements in telecommunications, looking further into the future presents even more complex challenges, particularly when considering the design and manufacturing of devices capable of operating at 300 GHz frequencies.
www.electronicsworld.co.uk February 2025 39
Manufacturing challenges and tolerances Manufacturing tolerances stand out as a significant hurdle when dealing with high-frequency designs. As frequency rises, the demands for tighter tolerances on component placement, interconnects and metalwork increase. Traditional manufacturing methods, such as CNC machining used to create the waveguide for signal conditioning, might lack the precision. Tis forces the adoption of new production methods such as additive manufacturing to achieve the required tolerances. Moreover, the journey from lower
frequencies to 300 GHz involves the development of smaller semiconductor features, especially for high-power devices. For compound semiconductor devices, this progress is slower due to limited demand and increased complexity. Te development of these processes is driven by the emergence of new applications and business cases, making it a lengthy and costly journey.
Integration and packaging challenges One of the paramount challenges in high-frequency design is the management of parasitics. A good example would be wire bonding at lower frequencies. The impact of parasitic elements can be mitigated with relative ease, but as we move to mmWave frequencies it becomes necessary to design a matching network to cancel out the parasitic effects. When we move to 300GHz this becomes impractical as manufacturing tolerances mean that a different matching network would be required for each new bond, clearly impossible in a volume production environment. To overcome these challenges, a shift
towards alternative packaging and interconnect solutions for semiconductor devices becomes imperative. Work has already started on such designs including flip-chip, hot vias and chip scale packaging.
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