Feature: RF Design
Table 1. Silent Switcher 3 Family Parameters
performance for any RFSoC system. Tis article will introduce several methods used in RF applications to achieve fast transient response in a power supply design.
How to achieve ultrafast power supply transient response for RF
applications By Xinyu Liang, Applications Engineering Manager, Analog Devices
S
ignal processing units and system-on-a-chip (SoC) units usually possess abruptly changing load transient profiles. Tis load transient will result in a disturbance on the supply voltage that is critical in radio frequency (RF) applications, as the clock frequency will be highly affected by the varying
supply voltage. As a result, RFSoCs usually apply blanking time during the load transient. In 5G applications, information quality is highly related to this blanking period during the transition. Tus, there is an increasing need to minimise the load transient effect on the power supply side to improve the system-level
34 February 2025
www.electronicsworld.co.uk
Fast transient silent switcher 3 family for RF applications One of the most straightforward methods to achieve fast transient power rails is to select regulators that feature fast transient performance. Te Silent Switcher 3 family of ICs features exceptionally low frequency output noise, fast transient response, low EMI emissions and high efficiency. It features an ultrahigh performance error amplifier design that can provide extra stabilisation even with an aggressive compensation. Te 4MHz maximum switching frequency enables the IC to push the control loop bandwidth to the mid-hundred kHz range in a fixed frequency peak current control mode. Te Silent Switcher 3 ICs that designers can select to achieve fast transient performance are listed in Table 1. Figure 1 shows a typical 1V output power supply based on the
LT8625SP for the 5G RFSoC, which needs fast transient response and low ripple/noise level at the same time. Te 1V load consists of both transmitted/received related circuits as well as local oscillators (LOs) and voltage-controlled oscillators (VCOs). Te transmitted/ received loads see abrupt load current change in the frequency division duplex (FDD) operation. At the same time, LOs/VCOs see constant load but require critical high accuracy and low noise. Te high bandwidth feature of LT8625SP enables designers
to power the two critical 1V load groups from a single IC by separating the dynamic load and static load with a second inductor (L2). Figure 2 shows the output voltage response with a 4A to 6A dynamic load transient. Te dynamic load recovers within 5µs with less than 0.8 per cent peak-to-peak voltage, which minimises the effect on the static load side with a less than 0.1 per cent peak-to- peak voltage. Tis circuit can be modified to accommodate other output combinations, like 0.8V and 1.8V, that can all directly supply the RFSoC load without the LDO regulator stage due to the ultralow noise in the low frequency range, low voltage ripple and ultrafast transient response. In time division duplex (TDD) mode, the noise critical LOs/
VCOs become loaded and unloaded together with the transmit/ receive mode changes. Tus, a simplified circuit as shown in Figure 3 can be used as all of the loads are considered to be dynamic load
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