Feature: Memory
Reducing the performance gap between DRAM and AI processors
By Allen Youssefi, Director of Product Management, Memory & Interface and Extended Enterprise Products, Renesas
D
RAM holds a unique place in the industry thanks to its cost, large storage capacity and ability to feed data and program code to the host processor quickly.
As high-performance FPGAs, CPUs,
GPUs, TPUs and custom accelerator ASICs meet the massive data processing demands of predictive and generative AI applications, DRAM’s role is becoming even more crucial. Te sheer compute density of these rapidly emerging AI accelerators is shattering even the most ambitious expectations, and the number of processor cores inside data centre servers continues to balloon. As advanced logic continues to scale,
DRAM has struggled to keep pace. Tis gap contributes to a widening performance mismatch between the two that can compromise server performance by forcing expensive processors to waste compute cycles while waiting for main memory to catch up.
Supercharging DRAM interface design Tis is a dynamic that has existed for some time. Te classic Von Neumann architecture model decouples of the processor and
memory, which creates a chokepoint that prevents designers from optimising every compute cycle. Tis situation requires a new approach to bring processors and memory into closer alignment. DRAM designers are rushing to close the
gap, working towards reaching higher speeds for both server and client memory modules to address the fast-changing requirements. Tat has motivated Renesas to recently launch a Multiplexed Registered clock driver (MRCD), Multiplexed Data Buffer (MDB), and PMIC to enable next-generation MRDIMM speeds up to 12,800 Mega Transfers Per Second (MT/S) for AI and High-Performance compute applications. Together with these new devices, Renesas is
also leading with memory interface devices for traditional data centres, client and embedded applications, making it the first and only complete memory interface chipset solutions in the industry. Tese new drivers enable a hierarchy of
memories operating at different performance, power and capacity levels. Teir adoption is expected to drive the growth of 'chiplets,' an emerging form of heterogeneous computing that converges components with different functions, process nodes and electrical
characteristics. Heterogeneous computing is also driving research into new approaches to memory and logic within the device and module, inside the server and across the entire server rack.
Ecosystem collaboration Working closely with the JEDEC standards body as well as partners within the industry on design, development, specification definitions and high-volume manufacturing, Renesas is facilitating an ecosystem of development partners that include DRAM and DIMM makers, CPU, GPU and other logic providers, server designers – even hyperscale computing operators. In addition to setting a shared roadmap and key performance indicators, this group ensures design verification and interoperability testing at the device, module and system level – and across all relevant soſtware applications. Ultimately, our goal at Renesas is to
empower device, module and system architects to break conventional design constraints. Together, we can unleash the potential of a co-optimised compute-memory architecture and better meet the needs of increasingly sophisticated – and compute- intensive – AI applications.
32 February 2025
www.electronicsworld.co.uk
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