Column: JESD204 standard
tightly controlled: the load resistance needs to be about 100Ω, usually achieved with a parallel termination resistor at the receiver. In addition, the LVDS signals must be routed using controlled impedance transmission lines. Te single-ended impedance required is 50Ω, whilst the differential impedance is maintained at 100Ω. Figure 2 shows a typical LVDS output driver. Tis figure shows that the circuit operation
results in a fixed DC load current on the output supplies. Tis avoids the current spikes seen in a typical CMOS output driver when the output logic state transitions. Te nominal current source/sink in the circuit is set to 3.5mA, resulting in a typical output voltage swing of 350mV with a 100Ω termination resistor. Te common-mode level of typically set to 1.2V, compatible with 3.3V, 2.5V and 1.8V supply voltages. Two standards have been written to define
the LVDS interface: Te most commonly used is the ANSI/TIA/EIA-644 specification entitled “Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits”. Te other is the IEEE standard 1596.3 “IEEE Standard for Low Voltage Differential Signals (LVDS) for Scaleable Coherent Interface (SCI)”. LVDS requires special attention to the
routing of signals but offers many advantages for converters sampling at 200MSPS or higher. Te constant current of the LVDS driver allows many outputs to be driven without the large current draw that CMOS requires. In addition, it is possible to operate LVDS in a double-data rate (DDR) mode, where two data bits can be routed through the same LVDS output driver. Tis reduces the number of pins required by half compared with CMOS; the power consumed for the same number of data outputs is also reduced. LVDS offers many advantages over CMOS
for converter data outputs, but, like CMOS, it also has limitations: As converter resolution increases, the number of data outputs required by an LVDS interface becomes more difficult to manage in PCB layouts. Eventually, the sample rates of converters push the required data rates of the interface beyond the capabilities of LVDS.
CML output drivers Te latest trend in digital output interfaces for converters is a serialised interface that uses CML output drivers. It is typically
used by converters with higher resolution (≥ 14 bits), higher speed (≥ 200MSPS), smaller packages and with low power consumption. Te CML output driver is used in JESD204 interfaces found in the latest converters. With the current revision of specification JESD204B, it allows data rates to 12Gbps on the converter outputs. In addition, the number of output pins required is significantly lower, with a minimum of two being required; see Figure 3. Routing a separate clock signal is no longer necessary, since the clock becomes embedded in the 8b/10b encoded data stream. As converter resolution, speed and channel
count increase, the number of data output pins may be scaled up to account for the bigger throughput. Since the interface used with CML drivers is typically serial, however, the pin numbers required are fewer than that of CMOS or LVDS (the data transmitted in CMOS or LVDS is parallel, which calls for a greater number of pins). Figure 3 shows the optional source
termination resistor and common-mode voltage. Te inputs to the circuit drive the switches to the current sources, which drive the appropriate logic value to the two output terminals. As with LVDS, a CML driver operates in
constant-current mode, which lowers power consumption. Tis requires fewer output pins, and total power consumption is reduced. Also, as with LVDS, load termination is
required, as well as controlled-impedance transmission lines with single-ended impedance of 50Ω and differential impedance of 100Ω. Te driver itself may also have terminations, as shown in Figure 3, to help with any signal reflections due to the sensitivity of such high bandwidth signals. In converters employing the JESD204 standard, there are different specifications for the differential and common-mode voltage levels, depending on the speed of operation. At speeds to 6.375Gbps, the differential voltage level is nominally 800mV, whilst the common mode is about 1V. At operating speeds above 6.375Gbps but below 12.5Gbps, the differential voltage level is specified at 400mV, whilst the common mode is again about 1V. With increased converter speed and resolution, CML looks to be the required driver type to deliver the speeds necessary to keep pace with the technology demands on converters for their various applications.
20 February 2021
www.electronicsworld.co.uk
Digital timing Each digital-output driver type has timing relationships that must be closely monitored. Since there are multiple data outputs with CMOS and LVDS, attention must be directed to the signals’ routing paths to minimise skew. If there is too large a difference, then proper timing at the receiver may not be achieved. In addition, there is a clock signal that needs to be routed and aligned with the data outputs. Careful attention must be paid to the routing paths between the clock output and data outputs to minimise the skew. In the case of CML in the JESD204 interface,
attention must also be directed to the routing paths between digital outputs. Tere are significantly fewer data outputs to manage, so this task becomes easier, but can’t be neglected. In this case, there should be no concern with regards to timing skew between the data and clock outputs since the clock is embedded in the data. However, attention must be given to adequate clock and data recovery (CDR) circuits in the receiver. In addition to skew, the setup and hold times must
also be considered with CMOS and LVDS: Te data outputs must be driven to their appropriate logic state in sufficient time before the edge transition of the clock, and must be maintained in that logic state for a sufficient time aſterward. Tis can be affected by the skew between the data and clock outputs, so it’s important to maintain good timing relationships. LVDS advantages over CMOS include lower
signal swings and differential signalling. Te LVDS output driver does not have to drive such a large signal to many different outputs and does not draw a large amount of current from the power supply when switching logic states, as with a CMOS driver. Tis makes it less likely to change logic states. If there are many CMOS drivers switching
simultaneously, the power supply voltage can get pulled down, introducing problems driving the right logic values to the receiver. Te LVDS drivers will maintain a constant level of current such that this particular issue should not arise. In addition, LVDS drivers are inherently more immune to common- mode noise, due to the differential signalling.
Adaptation As converter technology progresses with increasing speeds and resolutions, digital output drivers have adapted and improved to meet the requirements necessary to transmit data. CML outputs are becoming more popular as converter digital output interfaces transition to serialised data transmission. However, CMOS and LVDS digital outputs are still widely used, so there are applications best suited to each type.
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