Column: JESD204 standard


Digital data outputs in high-speed converters


By Jonathan Harris,


Product Applications Engineer, Analog Devices


W


ith many analogue-to- digital converters (ADCs) available for designers to choose from


today, an important parameter to consider is the type of digital data outputs provided. Currently, the three most common types of digital outputs used by high-speed converters are CMOS, low-voltage differential signalling (LVDS) and current-mode logic (CML).


CMOS digital output drivers In ADCs with sample rates below 200MSPS, it is common to find CMOS digital outputs. A typical CMOS driver consists of two transistors – NMOS and PMOS – connected


between power supply (VDD) and ground; see Figure 1a. Tis structure results in output inversion, so, to avoid that, it’s best to use the back-to-back arrangement of Figure 1b. Te CMOS output-driver’s input is high impedance whilst its output is low impedance. At its input, the impedance of the gates of the two CMOS transistors is quite high (ranging from kΩ to MΩ) since the gate is isolated from any conductive material by the gate oxide. At the driver’s output, the impedance is governed by drain current, ID


, which is typically small, in


this case lower than a few hundred ohms. Te voltage levels for CMOS swing from VDD


to ground, which means they can be quite large, depending on VDD


’s magnitude. As the input impedance is high and the


output impedance relatively low, with CMOS, one output can typically drive multiple inputs, and, also, static current is low. Te only instance during significant current flow is when the CMOS driver is switching. When the driver is in either low (pulled to ground) or high (pulled to VDD


), little current flows through it.


Figure 1: Typical CMOS digital output


However, when it switches from low to high, or vice versa, there is a momentary low resistance path from VDD


to ground. Tis transient


current is one of the main reasons why other technologies are used for output drivers when converter speeds rise above 200MSPS. A CMOS driver is also required for each bit


Figure 2: Typical LVDS output driver


of the converter: If a converter has 14 bits, 14 CMOS output drivers are required to transmit them. Commonly, more than one converter comes in a given package, with up to eight converters in a single package. With CMOS technology this means up to 112 output pins required just for the data outputs. Not only is this difficult from a packaging standpoint, it also consumes more power and increases layout complexity. Tis is why an interface using LVDS was introduced.


LVDS digital output drivers LVDS offers several advantages over CMOS: It operates at a lower voltage (approximately 350mV), and is differential rather than single- ended. Te resultant lower voltage swing has a faster switching time and reduces EMI. By virtue of being differential, there is also


Figure 3: Typical CML output driver


18 February 2021 www.electronicsworld.co.uk


the benefit of common-mode rejection. Tis means that signal-coupled noise tends to be common to both signal paths and is mostly cancelled out by the differential receiver. However, the LVDS impedances must be more


Page 1  |  Page 2  |  Page 3  |  Page 4  |  Page 5  |  Page 6  |  Page 7  |  Page 8  |  Page 9  |  Page 10  |  Page 11  |  Page 12  |  Page 13  |  Page 14  |  Page 15  |  Page 16  |  Page 17  |  Page 18  |  Page 19  |  Page 20  |  Page 21  |  Page 22  |  Page 23  |  Page 24  |  Page 25  |  Page 26  |  Page 27  |  Page 28  |  Page 29  |  Page 30  |  Page 31  |  Page 32  |  Page 33  |  Page 34  |  Page 35  |  Page 36  |  Page 37  |  Page 38  |  Page 39  |  Page 40  |  Page 41  |  Page 42  |  Page 43  |  Page 44