Focus: FeRAM
FeRAM poised to unlock denser, more-effi cient Edge AI memory
By Simon Martin, R&D Engineer in electrical characterisation, CEA-Leti C
EA-Leti demonstrated a ferroelectric RAM (FeRAM) scaled to the 22nm manufacturing node. The breakthrough removes a longstanding density barrier
that has kept FeRAM from competing with volatile memory, and opens the door to faster, more energy-efficient artificial intelligence (AI) at the edge. CEA-Leti researchers used an innovative 3D capacitor
architecture for the technology. By vertically integrating ferroelectric capacitors made from hafnium zirconium oxide (HZO) thin films, the team achieved memory cells that are 2.5 times smaller than standard SRAM at the same 22nm node, matching the density of SRAM at the much more advanced 10nm node. Moreover, unlike SRAM, FeRAM retains data without power, combining non-volatility with a density previously attainable only by volatile memory.
Processor embeddable Today’s smart devices increasingly rely on sending data to the cloud for AI processing, which adds cost and time. FeRAM is both fast and dense enough to embed directly on a processor, allowing devices to process data locally. The implications extend beyond user convenience:
computing operations account for a significant and growing share of global electricity consumption, much of it still generated from fossil fuels. Thus, FeRAM paves the way for highly energy-efficient systems, helping to reduce overall power consumption and lower reliance on fossil-based energy sources.
What’s new? Historically FeRAM fabrication was constrained to flat, planar capacitor structures that limited how small and dense memory cells could be made. In these architectures, the capacitor – not the selection transistor – determines the cell footprint, because the current flowing through the capacitor during memory operations is inherently low. To overcome this physical limit, CEA-Leti shifted to a
vertical architecture, building the capacitor upwards rather than outwards. The team demonstrated two back-end-of-line (BEOL)
08 September 2026
www.electronicsworld.co.uk
Figure 1: 3D HZO FeCap based FeRAM array integrated at 22nm FDSOI node features 0.047µm2
1T1C bitcell size with NMOS transistor
integration schemes for 3D ferroelectric capacitors (FeCaps) at 22nm, applying advanced patterning and deposition techniques; see Figure 1. Array functionality with Gaussian bit distributions was confirmed down to 0.047μm² 1T-1C FeRAM bitcells, operating at just 1.3V and featuring a standard logic selector as well as a 3D FeCap with an aspect ratio of roughly 4:1.
The researchers also demonstrated a clear path to even
greater density: 3D FeCaps with an aspect ratio of 17:1, a 60nm diameter and a 120nm pitch, shrinking the capacitor footprint to just 0.0028μm²; see Figure 2. A higher aspect ratio maximises the effective surface area
Page 1 |
Page 2 |
Page 3 |
Page 4 |
Page 5 |
Page 6 |
Page 7 |
Page 8 |
Page 9 |
Page 10 |
Page 11 |
Page 12 |
Page 13 |
Page 14 |
Page 15 |
Page 16 |
Page 17 |
Page 18 |
Page 19 |
Page 20 |
Page 21 |
Page 22 |
Page 23 |
Page 24 |
Page 25 |
Page 26 |
Page 27 |
Page 28 |
Page 29 |
Page 30 |
Page 31 |
Page 32 |
Page 33 |
Page 34 |
Page 35 |
Page 36 |
Page 37 |
Page 38 |
Page 39 |
Page 40 |
Page 41 |
Page 42 |
Page 43 |
Page 44
