Feature: Power management
Adapting
LPDDR memory technology for AI workloads
T
By John Eble, VP of Product Marketing, Memory Interface Chips, Rambus This has sparked interest in low
he acceleration of artificial intelligence (AI) workloads is reshaping how modern data centres are designed. By 2030 it is
expected that AI will drive nearly 70% of the total demand among data centre capacity. While advances in central processing units (CPUs) and AI accelerators have enabled dramatic gains in processing capability to reach this surge, the industry is now facing critical bottlenecks in memory systems as AI server architectures become increasingly power and thermally constrained. Ultimately, these constraints limit scalability and overall system performance. The need for AI training and
inference workloads to continuously move large datasets between memory and compute significantly increases throughput demands across AI infrastructure. Since processors are scaling faster than memory subsystems can support, memory bandwidth is becoming the main factor limiting increases in throughput.
power double data rate (LPDDR) as an alternative server memory technology to better align with the needs of AI-driven workloads. While DDR memory delivers superior capacity, latency and RAS (reliability, availability and serviceability), LPDDR, which was originally developed for battery-operated mobile devices, offers compelling power efficiency advantages for bandwidth-intensive data processing. With higher bandwidth per watt, LPDDR can offer a more power- efficient approach to supporting AI- driven data centre workloads.
LPDDR into AI servers Whilst LPDDR promises substantial benefits for AI servers, realising that promise in data centre environments has challenges. In mobile phones, LPDDR devices are designed to be either co-packaged with the processor, or adjacent to it. This layout minimises trace lengths and preserves signal integrity required for high-speed operation. In addition, with mobile phones
20 September 2026
www.electronicsworld.co.uk
there is generally no need to replace the memory. Due to trace length limitations, simply mounting LPDDR devices in traditional slotted server modules is not feasible. Longer trace lengths and losses traversing the socket would reduce signal integrity to an unacceptable level. Also, in server applications, in general it is important to be able to replace the memory, for serviceability and upgradeability. Therefore, the transition from mobile to data centre environments creates a significant architectural gap.
SOCAMM2 bridges the divide Transitioning LPDDR from battery- operated mobile devices to AI servers requires a new memory module architecture that translates both efficiency and bandwidth advantages into power-constrained, high- performance data centre environments. That’s why SOCAMM2 (small outline compression attached memory module 2) was developed. SOCAMM2 is a JEDEC-standardised LPDDR server module specifically designed to accommodate AI infrastructure.
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