Column: Silicon systems design
historically separated by tools, scripts and manual hand-offs. It can keep investigations moving, perform repeatable analysis and allow engineers to explore more options within limited schedules. But one distinction must remain clear:
execution autonomy is not sign-off authority. An agent may plan, generate tests, invoke tools, analyse results and propose the next step, it should not independently decide that a design has been sufficiently verified. A better future is not an autonomous
system declaring a chip correct, but a controlled engineering environment in which agents accelerate the route from specification to evidence, whilst engineers retain ownership of intent, methodology, risk acceptance and final sign-off. Tat balance will determine whether
verification agents create measurable engineering capability or simply more automated activity.
Agentic-based DV EDA products Several agentic-based DV EDA products are already emerging in the market. Cadence’s ChipStack AI Super Agent coordinates specialised agents across RTL generation, verification planning, testbench creation, regression orchestration and debug. Synopsys AgentEngineer applies coordinated agents to multi-stage engineering workflows spanning specification, implementation and verification. Te Questa One Agentic Toolkit by Siemens provides agents for RTL creation, verification planning, lint, clock-domain-crossing analysis and debug. MooresLab AI’s VerifAgent focuses on specification-driven UVM verification, including the generation of testbenches, scoreboards, assertions and coverage collateral. AlpinumDV can currently generate verification plans, UVM testbench
components, assertions, coverage models and supporting verification collateral. It also supports testbench validation, mutation testing, dynamic stimulus generation and coverage closure. Te next release will extend these capabilities to full SoC design verification, encompassing bus fabric, bridge, peripherals and soſtware- driven verification. Te Submission Portal provides a controlled environment for submitting verification jobs and reviewing the resulting logs and evidence. Tis positions AlpinumDV as a practical agentic verification environment that progresses from specification-driven asset generation towards coordinated SoC-level verification, whilst retaining traceability, engineering review and human sign-off authority.
Tis column continues in next month’s edition of Electronics World
www.electronicsworld.co.uk September 2026 15
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