Embedded Technology


Taking a closer look at Cycle- resolution Timing


By Bianca Schmidt, technical writer at SEGGER Microcontroller W


hen developing embedded systems, selecting the


appropriate real-time operating system (RTOS)


is essential to ensuring efficient and reliable operation. When comparing the available RTOS scheduling options, Cycle-resolution Timing (CRT) stands out because of its unique approach.


This article takes a closer look at the differences between super- loop architectures, traditional real-time operating systems, and an RTOS – SEGGER’s embOS-Ultra – that uses Cycle-resolution Timing. It details this distinct approach and compares it to other approaches when it comes to developing applications for embedded systems.


Differences between a super-loop architecture, a standard RTOS, and an RTOS using Cycle-resolution Timing


To better understand Cycle-resolution Timing, it is essential to compare it with super-loop architectures and standard real- time operating systems.


Super-loop architecture


A super-loop architecture, also known as “bare-metal programming,” does not use any kind of real-time operating system. In this architecture, the system continuously checks the operating states without using any scheduling mechanism. This constant checking adds unnecessary processing load and consumes device power. Moreover, the lack of scheduling restricts the system’s effectiveness in managing tasks.


Approach of standard real-time operating systems


In contrast to the super-loop approach, a standard real-time operating system takes care of tasks and resource management. It also uses periodic system tick interrupts generated by a hardware timer as both the time base for the RTOS and for scheduling.


70 September 2023


Figure 1: Difference between an RTOS using cycle-resolution timing (bottom) and a conventional RTOS (top). The CPU stays in energy-saving mode significantly longer and is woken up less often by interrupts (red), resulting in more computing power and less energy consumption.


While this improves task management compared to a super-loop architecture, it still requires periodic checks to identify pending tasks. In most applications, the system tick interrupt occurs every millisecond and continues to occur even when the system is idle or no other task is scheduled. It therefore wastes computing time when no time-based action is required for multiple consecutive system ticks. For an RTOS that does not use Cycle- resolution, a SysTick event with no pending task causes an “empty” interrupt. The existence of “empty” tasks or interrupts has several implications for the application. Firstly, they unnecessarily burden the processor, leading to increased usage and higher energy consumption. Additionally, these interruptions can be disruptive, especially in the context of signal processing. For instance, when a signal is being generated and an interrupt interferes with the process, it introduces a time delay of approximately 5 µs. This is due to task switching time, depending on the real-time operating system, and the microcontroller or processor used. This delay primarily


Components in Electronics


restricts the bandwidth at which the system can generate signals.


The problem is that interrupts do not always cause disruptions, making it difficult to attribute signal instabilities solely to them. This complexity poses challenges during debugging, particularly when using the step-by-step execution mode (single- step mode) where such interrupts often go unnoticed.


In a traditional RTOS that uses periodic system tick interrupts as both the time base and for scheduling, all timeouts, delays, and periodic timers need to be specified in system ticks instead of an amount of time. This means that they are always aligned with the periodic system tick interrupt, severely limiting the resolution for scheduling events. When tasks need to be executed at times that do not align with the System Tick, traditional RTOSs can only do this by either waiting or utilizing extra resources – if they are available at all. Waiting imposes unnecessary strain on the system. Allocating additional resources, such as another timer interrupt, could potentially introduce additional side effects or computational load.


Cycle-resolution Timing explained An RTOS using Cycle-resolution Timing however, is active when a change necessitates the operation of the RTOS. The system precisely determines when to awaken to fulfill its tasks and allocate resources to pending assignments. There’s no need to continually poll for events, consistently or intermittently, via the SystemTick. Instead, it leverages the cycles of an ongoing hardware counter that runs continuously, serving as the fundamental time base for the RTOS. With the option of CRT, the RTOS has flexible system tick interrupts available to precisely schedule any future task without further side effects. Thus, they can be specified in system-independent, high-resolution units such as milliseconds, microseconds, or even hardware counter cycles instead of system ticks.


This new cycle-resolution timing approach makes it possible to schedule task switches precisely, thus enabling the shifting of tasks into the real-time operating system that would traditionally be programmed outside of it. This applies to tasks shorter than the system tick as well as tasks that do not need to be scheduled


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