Semiconductors
can support fi ne routing, provides material advantages such as tuneable coeffi cient of thermal expansion, and is compatible with large-area panel processing. However, glass- based packaging remains at an early stage of commercialization. The key questions are not only whether glass can deliver attractive electrical and mechanical properties, but whether manufacturing processes can scale reliably, and whether the broader ecosystem is ready to support high-volume adoption. On the manufacturing side, challenges remain in through-glass via formation, metallization, large-panel handling, inspection, warpage control, reliability qualifi cation, and cost-effective production. On the ecosystem side, wider adoption will depend on the readiness of material suppliers, equipment vendors, substrate manufacturers, foundries, OSATs, and design-tool providers to support glass-based packaging at commercial scale.
4 Hybrid bonding
Compared with conventional microbump- based interconnects, copper-copper hybrid bonding enables fi ner interconnect pitch, lower parasitic resistance and capacitance, and higher vertical interconnect density between stacked dies.
The technology is already used in several high-end products. Examples include AMD’s 3D V-Cache, which stacks SRAM on CPU dies in its EPYC data centre processors, and the MI300 series, which also uses hybrid bonding technology to stack CPU/GPU tiles on I/O dies. Intel is also adopting its own 3D hybrid bonding technologies for next-generation server CPUs.
Beyond logic stacking, hybrid bonding is expected to become increasingly important for memory. As HBM moves beyond 16-Hi and 20-Hi stacks, conventional stacking and bonding approaches will face growing challenges in interconnect density, stack height, and thermal performance. Hybrid bonding is therefore being expected as a key route for future high-density DRAM stacking. Hybrid bonding also plays a key role beyond processor and memory integration. In co-packaged optics, it can be used to integrate electronic ICs with photonic ICs. This makes hybrid bonding a cross-cutting technology across computing, memory, and optical interconnects.
5 Co-packaged optics
Co-packaged optics is emerging as an important advanced semiconductor
packaging opportunity as data centres require higher bandwidth and greater power effi ciency. In conventional pluggable optics, the optical engine is located at the front panel and connected to the switch ASIC through long Cu traces on PCB. As switch bandwidth increases, these electrical paths become increasingly constrained by signal loss, power consumption, connector density, and thermal limits. Similar optical I/O concepts are also being explored for accelerator systems, where optical engines could be integrated closer to GPUs or other compute dies. In fi rst-generation CPO architectures, 2.5D packaging can integrate optical engines on the same package substrate as the main compute or switching die, reducing electrical path lengths from tens of centimetres to a few millimetres. Next- generation CPO architectures may further shorten interconnects by packaging optical engines together with the compute die on an interposer.
Advanced semiconductor packaging therefore plays a central role in CPO by enabling dense electrical routing, shorter die-to-optical-engine connections, and integration of EICs, PICs, interposers,
redistribution layers, and fi bre-attach structures. However, the packaging challenge also increases. Optical alignment, fi bre-to- chip coupling loss, thermal management, testability, repairability, assembly yield, and long-term reliability remain key barriers to scalable adoption.
In summary, advanced semiconductor packaging is becoming a critical enabler for AI and HPC systems, as performance increasingly depends on system-level integration rather than chip performance alone. The continued development of 2.5D and 3D advanced packaging technologies will be essential for improving bandwidth and power effi ciency at the system level, while also creating new technical challenges across manufacturing, thermal management, optical coupling, and supply chain readiness, especially for emerging material platforms. To learn more about these technology trends and market opportunities, please refer to IDTechEx’s report, “Advanced Semiconductor Packaging 2027-2037: Forecasts, Technologies, Applications.” For more information on this report, including downloadable sample pages, please visit:
www.IDTechEx.com/ASP
microchip.com/pic32cm-pl10
www.cieonline.co.uk
The Microchip name and logo and the Microchip logo are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. All other trademarks are the property of their registered owners. © 2026 Microchip Technology Inc. All rights reserved. MEC2640A-UK-01-26
Components in Electronics
October 2026 29
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