Semiconductors


Key technology trends to watch in advanced semiconductor packaging


By Dr Yu-Han Chang, principal technology analyst, IDTechEx A


dvanced semiconductor packaging has become a central technology platform for high-performance computing. For AI and HPC processors,


performance depends not only on transistor density, but also on memory bandwidth, I/O density, power delivery, thermal management, and the ability to integrate more functional dies within a single package.


This is driving the continued adoption of 2.5D and 3D packaging architectures. In 2.5D packaging, chiplets are integrated side by side on an interposer/redistribution platform. In 3D packaging, active dies are stacked vertically using technologies such as hybrid bonding. Together, these approaches enable heterogeneous integration across different chiplets, bring memory closer to compute, increase die-to-die interconnect density, shorten electrical paths, and support the integration of optical and electrical components within the same package. This article explores the technology development trends in advanced semiconductor packaging technologies. The insights are derived from IDTechEx's recent report, "Advanced Semiconductor Packaging 2027-2037: Forecasts, Technologies, Applications,” which delves deep into understanding the technical aspects of packaging technologies, examining industry challenges, the progress made by leading companies, and providing market forecasts for the sector.


Key trends in 2.5D and 3D packaging development to watch 1 Larger package areas


One of the clearest trends in advanced semiconductor packaging is the continued increase in package size. AI and HPC systems require more compute dies, I/O dies, and HBM stacks to be integrated within a single package to improve system-level performance. As a result, the industry is moving toward


28 October 2026


Evolution Roadmap of Semiconductor Packaging. Source: IDTechEx


interposer and substrate platforms that can scale package area while maintaining high interconnect density.


TSMC’s CoWoS roadmap illustrates this direction. In 2026, TSMC is already in volume production of a larger 5.5× reticle-scale CoWoS_L platform (Si bridge platform), targeting large multi-die architectures with high-end compute tiles, multiple I/O dies, and up to around 12 HBM3E/HBM4 stacks. By 2027, further scaling toward approximately 9.5× reticle-scale packages is expected to enable even larger compute and memory configurations.


This scaling trend is also changing the interposer technologies being adopted. Full silicon interposers have supported the current generation of high-performance AI accelerators, but their scalability is constrained beyond around 3.3× reticle size due to yield, cost, and manufacturability challenges. As a result, bridge-based architectures and glass-based platforms are


Components in Electronics


gaining attention as the industry seeks to extend 2.5D integration without relying on full-area silicon interposers.


2 Panel-level packaging


Panel-level packaging is being explored as a route to larger and more cost-effective advanced packages. By moving from circular wafers to rectangular panels, manufacturers can improve area utilization and therefore enable higher throughput and reducing packaging cost per AI accelerator. However, the transition remains technically challenging. As panel sizes scale from early development formats around 310 × 310 mm toward larger formats such as 510 × 515 mm or 620 × 750 mm, manufacturing becomes more difficult.


Key challenges include warpage control, finer RDL formation, yield management, standardization, thermal management, full panel uniformity, and so on. These factors directly affect yield, interconnect reliability,


and the ability to manufacture fine-pitch redistribution structures at scale. Commercial adoption will therefore depend on whether the industry can convert large-area processing advantages into stable, high-yield manufacturing.


3 Glass interposers and glass core substrates


Glass is emerging as a key materials platform for next-generation advanced semiconductor packaging, driven by the limitations of both organic substrates and silicon-based interposers. Organic substrates are well established and cost-effective, but face challenges especially in fine-line routing and warpage as package size increases. Silicon- based interposers offer high interconnect density, but their scalability is constrained by reticle limits, wafer utilization, and cost, particularly as AI accelerator packages continue to grow.


Glass offers a potential middle ground. It www.cieonline.co.uk


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