FEAT RE FEA ATURE


DISPLAYS &


YS & UIS AUTONOMOUS CROWD MONITORING


ADVANCES MODERN AGE OF HMI Muhammad Bilal & Dr. Shoab. A. Khan, Centre for Advanced Studies in Engineering investigate how the latest Xilinx FPGAs are advancing autonomous monitoring of crowds in busy public environments


C


rowd surveillance andmonitoring has gained crucial importance in recent


years. Governments and security agencies are looking formore advancedways to intelligentlymonitor human crowds across public places to detect any unusual activity before it is too late to react.


Manualmethods alone cannotmonitor all possible crowd activities from thousands of CCTV cameras across a whole city, 24 hours a day. However, intelligent cameras or vision systems that autonomouslymonitor the activities of human crowds through ad vanced video analytics techniques promise the ability to provide timely reports on any unusual event to a central control station. Such intellige


gent camera/vra/vision systems re


require powerful video processors on board to achieve


rd ve the high processing requirements


rformance-hungry applications. This is amply demonstrated by a newprototype for a human crow


of sophisticated video analytics techniques. FPGAs are ideally suited to such perf


owdmotion-classification and


monitoring systemusing VivadoHLS, Xilinx’s EmbeddedDevelopment Kit (EDK) and software-based EDA Design Suite.


rv DAtools fromthe ISE


Typical algorithms for crowd surveillance andmonitoring startwith detecting (or placing) interest points in the human crowd scenes, tracking themover time to collectmotion statistics. A template- matching scheme formotion estimation offers advantages over alternative


feature-tracking approach es. In particular, it excels overmotion estimation in cases of lowor varying contrast - albeit at the cost of a fewmore computations.


The video frame is divided into a grid of smaller rectangular patches, andmore than 900motion vectors are computed across thewhole image. The algorithm then computes statistical properties such as averagemotion vector length, number ofmotion vectors, dominant direction of motion and similarmetrics.


Statistical properties acrossmultiple frames allowthemotions to be classified. For example, ifmotion is ob rvserved to be high and there is a sudden change in momentumin the scenewhile the direction ofmotion is randomor out of the image


ge plane, then it can be classified as possible panic behaviour. 8 OC OB OCTOBER 201 2016 | ELEC RO ELECTRONICS CS FPGA MPLEMENTA FPGA I IMPLEMENTATIONATION


Key challenges for FPGA implementation include the integration of video input/output and frame buffering as part of FPGA-based design. A real-time video pipeline hides the complexmemorymanage


gement related to


video input/output and frame buffering from the user, and provides a simple interface for accessing video frame data for processing. A customised video pipeline built around the Xilinx EDK provides capture/display ports for handling video data and is easily configurable for other FPGA families. Video input and output ports are connected to the main peripheral bus of aMicroBlaze host processor,which handles video data traffic to and fromthemainmemory.


There are several benefits of using a MicroBlaze as a host processor to


interconnect various building blocks in the system. It is easy to interface awide range of externalmemories (SRAM, SDRA withMicroBlaze f video frame data DMAcontro


RA rollers can be used in the EDKfor transporting data between video ports and ge RAM, etc.)


fromvideo ports. Similarly, or loading or storing the


Figure 1: Figure 1:


Steps in computing motion vectors, starting with image capture (top)


Steps in computing


motion vectors, starting with image capture (top)


mainmemory.An ana gous approachis used to interf


logo rface customhardware rd


acceleratorswiththe processor. Themost time-consuming and


computationally intensive task here is to computemotion ve


vectors. Ahardware


accelerator, synthesised in RTL using Xilinx’s VivadoHLS in C/C++, produces highly optimised code. VivadoHLS synthesises array accesses (such as pixel data) into memory interfaces and automatically generates re


ge require red a dred resses by analysing


the code. It also analyses pre-computable offsets and constants to perf “strided”memory accesses. Eight Block RA


load and store video frame data in parallel. The hardware accelerator core can compute fourmotion vectors in parallel, and for this purpose it utilises all eight BRA


RAMs (BRAMs) are used to ra


RA RAMs.


The resulting hardware accelerator operates at 200MHz and all processing needed to computemotion vectors across thewhole image completes in less than 10ms, including all data transfers to and frommemory.


Implementing algo gorithmcontrol and


data flowin the Xilinx SDK brings a large degree of flexibility to design, because it is possible to design and integrate new hardware accelerators in the same fashion, andmodify necessary control and data flowto incorporate newhardware


accelerators. This approach combines the flexibility of all-software implementation with the high performance of an all- hardware implementation .


Comparison of the resulting FPGA GA-based


implementationwith an earlier desktop PC- based implementation has demonstrated identical results. Thiswas achieved using only 30percent of the Spart Progra


rtan-6LX45All


60percent of BRA DSP48Emultiplier re


rammable FPGA’s slice lookup tables, RAMand 12 percent of resources.


Such results showthe huge potential in implementing performance-critical


applications over FPGAs using these tools. The benefits of fast and efficient


development could be extended to traffic monitoring, patient observ


rvation in hospitals andmanymore applications. Xilinx


www.xilinx.com T: 01932 574600


www.xilinx.com / ELECTRONICS ELECTRONICS rformvery fast


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