EA-Leti is collaborating with Intel on 3D and packaging

technologies for processors to advance chip design. The research will focus on assembly of smaller chiplets, for improved interconnection technologies between the different elements of microprocessors, and on new bonding and stacking technologies for 3D ICs, especially for making high performance computing (HPC) applications. Why it matters: 3D technology,

which stacks chips vertically in a device, not only optimises the power of the chip with advanced packaging interconnects between components, but it also allows the creation of heterogeneous

integration of chiplets. This ultimately allows fabrication of more efficient, thinner and lighter microprocessors. In addition, by implementing

multiple heterogeneous solutions in a single package, chip companies benefit from considerable flexibility, such as mixing and matching different technology blocks with different IP and integrating memory and input/ output technologies within the same component. This enables chip makers to continue to innovate and adapt to the needs of their customers and partners. In 2019, Intel introduced a 3D-

stacking technology, Foveros, that adapted these design features. This

advanced-packaging technology, launched in Intel Core Processors with Intel Hybrid Technology (named Lakefield), comes in a small physical package for significantly reduced board size to offer an optimal balance between performance and energy efficiency. At June 2020’s IEEE Electronic

Components and Technology Conference, CEA-Leti received the best paper award for its work, carried out at IRT Nanoelec, on silicon active interposer as a promising solution towards 3D heterogeneous integration. These results pave the way to future high efficiency systems for high performance computing.


ith the November issue we bring you some of the latest


Deep tech 3D perception platform start-up CronAI has partnered with Ouster, to support its current spinning lidar sensors and solid-state lidar. CronAI’s senseEDGE platform - a self-optimising, 3D data, deep learning edge inference perception processing platform – enables innovators to develop intelligent solutions using 3D sensors to accurately perceive the real world. The partnership provides Ouster’s partner and customer communities with early access to CronAI’s perception platform,

thereby enabling their teams to bridge the gap between complex 3D sensor data perception algorithms and real world applications on the product edge. “This partnership is significant, representing collaboration between a leader in lidar sensor technologies and

an AI Software & Hardware platform for 3D Perception,” said Tushar Chhabra, co-founder and CEO at CronAI. “Our heterogeneous software platform is specifically designed for processing 3D sensor data and for computer vision, and through our work together, Ouster can focus on building quality sensor technologies while their customers can significantly mitigate their investment risks. We’ve architected our platform to leverage the features of FPGAs supporting sequential, parallel and mixed workloads at lower precisions. That all adds up to improvement in throughput, lower latency and reduced power consumption. Now innovators can develop solutions using 3D sensors without the performance bottlenecks of traditional GPU compute hardware.”

technical innovations, starting with a focus on automotive electronics with a look at why ADAS functions require new integrations, on p16. 6SigmaET discusses top automotive thermal trends and how they are changing the face of electronics design on p18. Omron Electronic Components Europe explores effective remote thermal management of electrical systems on p20. On p22 we look at how Kuka’s mobile robot has revolutionised the semiconductor manufacturing process, using image processing, for transporting highly sensitive wafers, with support from Cognex. EU Automation, shares a seven steps approach to effective obsolescence management on p24. Continuing our focus on obsolescence NAD explains how its modular design construction technology keeps pace with industry innovation, on p26. ZF discusses how its sub-

subminiature switches are being used in electronic toll collection, on p28. Anders explains how self- sanitising touchscreens could help organisations resume commercial activities and mitigate virus transmission, on p30. In our embedded focus we look at industry collaboration on p32. Michelle Winny Editor


Congatec has introduced new application-ready platforms for tactile Internet applications over public broadband as well as private IP networks. They support Time Sensitive Networking (TSN) in combination with the new Intel Time Coordinated Computing (Intel TCC) technology, which complements the TSN Ethernet standard based on latest Intel IP technology. The goal is to reduce latency and minimise jitter in real-time synchronised processes. The demo platforms enable tactile Internet applications on the basis of open Internet standards, finally paving the way for IP based real-time communication and real-time control infrastructures. Above all, such platforms are perfect for the digitisation of process industries, critical infrastructures and Industry 4.0 environments but also have the potential to heavily disrupt proprietary industrial Ethernet and fieldbus setups. The

major benefit is that open standard IP protocols can be utilised across all layers of the automation pyramid to communicate in real-time – from the highest level of operator dashboards down to a single I/O connected with the IIoT, and from a single sensor to the actor. The ready-to-use platforms are based on COM Express Type 6 modules with either 11th Gen Intel Core processors (Tiger Lake) or Intel Atom x6000E

Series processors (Elkhart Lake) and offers Ethernet connectivity with TSN support via multiple Gigabit Ethernet or 2.5 GbE ports. New are the added TCC support and additional time stamp counter (TSC) functions, which manage the synchronised execution of operations down to the I/Os in real-time.


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