FEATURE COVER STORY PhotoMOS relay technology
Advances in Panasonic PhotoMOS relay technology
possible. In reality this means keeping the load current to the minimum levels required to operating the subsequent circuitry. A typical temperature rise from 40˚C to 60˚C can result in an on- resistance increase by as much as 30% in this type of PhotoMOS relay. MOSFETs with higher load voltage
specifications have higher values for the on-resistance but can offer lower capacitance values and so improve the high frequency characteristics and decrease the switching loss levels. A number of devices are manufactured with different characteristics so that the circuit designer may chose the optimum device for the specific application. In many applications the push to
Panasonic outlines the most important advantages of the PhotoMOS range T
he ubiquitous electromechanical relay has been around for over 120 years and
despite some technical innovation utilises the same basic method of operation as originally designed. Despite the fact that this is still the mainstay of many electrical switching circuits it does suffer from some very obvious limitations in terms of size, coil power requirements and speed of contact operation. Some 30 years ago Panasonic introduced
a fully solid state switching product known as the PhotoMOS relay. This product was developed in order to offer the market an alternative to the standard electromechanical based signal switching relays that, although generally offered very good switching characteristics, were not ideal in applications that needed high operational life factors, high switching speed and very small board layout space. In design terms the input side of a PhotoMOS relay consisted of a LED diode which emitted light when a control current (typically down to 5mA) was applied to the input (equivalent to coil in an electromechanical relay). After passing through an isolating silicon resin the light was detected by an array of light sensitive cells leading to a voltage drop across the array output. The voltage drop was used to control two source coupled MOSFETs thereby switching the output from the on to off state and vice-versa, providing a practically infinite life operation within the MTBF factor of the relay. The structural design of a MOSFET dictates that the values of breakdown
12 MAY 2017 | ELECTRONICS
voltage, on resistance and output capacitance closely correlate with each other. The breakdown voltage is determined by the layout of the Drain to Body diode junction and it is this area that is also mainly responsible for the on- resistance of the device. The length of the cross sections and chip surface form a capacitor that leads to the marked parasitic capacities, influencing the relays switching times and isolation characteristics applied to high frequency signals. By redesigning the layout of a conventional MOSFET device it is possible to allow a reduced area junction ‘guard ring’ region that lowers the on-resistance and capacitance to an minimal level not previously achievable. There is a trade-off in the lowering on the maximum load voltages permissible, but this is usually a secondary requirement in the signal switching environment. Typical values for a CxR PhotoMOS are below 10Ω on- resistance and an output capacitance of 1pF leading to switching times of 20µS while more specialised CxR10 versions offer on resistances below 1Ω. In addition to the electrical
characteristics the temperature range must also be considered. The mobility of electrons within the MOSFET junctions decreases with rising temperatures and in turn this implies that the on-resistance will inversely increase. The circuit designer must ensure that if the application requires a high level of stability in terms of the on- resistance characteristic the operating temperature must be kept as low as
The latest additions to the PhotoMOS range should allow the circuit designer the maximum flexibility possible with the highest specification devices now being available in the smallest package design
miniaturise has left the circuit designer with the unenviable task of trying to reduce board space to an absolute minimum. PhotoMOS relays lend themselves very well to miniaturisation when compared with their electromechanical counterparts. The use of single wafer silicon substrates has allowed a dramatic reduction in size. Package designs such as SSOP ( shrink small outline package) has an area of only 60% compared to the previously smallest SOP (small outline package). If several relays are used in a system the SSOP saves a significant amount of space. An alternative solution is to utilise a SOP device that contains up to 4 individual relays. If smaller package sizes are required then Panasonic’s newly introduced VSSOP package offers switching in just 16% of the area occupied by the SOP package. Measuring just 2mm x 2mm the VSSOP package makes an ideal switch for testing and measurement applications where high density component mounting is needed. Smaller still is the TSON (ultra small
package) offing switching in less than 10% of the size of the SOP package but capable of 1.5A peak load switching at 30VDC. To summarise the most important advantages of PhotoMOS to the circuit designer: Linear output characteristics Low operating current (below 0.3mA available) Low output capacitance (RF types below 1pF ) Minimum leakage currents (pA) Extremely long lifetime Stable ON resistance over full lifetime Extremely compact design No contact bounce Highly resistant to shock and vibration factors No restrictions on mounting orientation Multiple contact versions.
Panasonic
www.panasonic-electric-works.com/uk/ T: 01908 231555
/ ELECTRONICS
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