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COVER STORY ADVERTISEMENT FEATURE


system without touching any of the low level interfaces. The LIDAR DAQ board shows how to design the power, clocking, and data interface for a JESD204B data acquisition system operating in Subclass 1 mode, ensuring deterministic latency so that zero sampling uncertainty can be achieved, while taking advantage of all the benefits that the JESD204B interface provides and having the lowest possible power for the clocking scheme. To operate in JESD204B Subclass 1 mode, there is a total of five clocks needed in the system: • ADC sampling clock: drives the ADC signal sampling process.


• ADC and FPGA SYSREF: source synchronous, high slew rate timing resolution signals responsible for resetting device clock dividers to ensure deterministic latency.


• FPGA global clock (also referenced as core clock or device clock): drives the output of the JESD204B PHY layer and FPGA logic.


• FPGA reference clock: generates the PHY layer internal clocks needed by the JESD204B transceivers; needs to be equal to or an integer multiple of the device clock.


All the clocks are generated by one AD9528 JESD204B clock generator, thus ensuring they are all synchronised with each other. The AFE board receives the optical reflected signal, converts it to an electrical signal, and transfers it to the ADC on the DAQ board. This board is probably the most sensitive part of the entire design since it mixes signal condition circuits working with microampere current signals generated by the 16-channel APD array, converting the optical signal to an electrical signal, with high voltage power supplies in the range of –120V to –300V needed to power the same APD. The 16 current outputs are fed into four low noise, four-channel, transimpedance amplifier (TIA) LTC6561s with an internal 4-to-1 mux to select the output channel that is afterward fed into one of the four ADC inputs. The input section of the TIAs needs a lot of attention to achieve the desired level of signal integrity and channel isolation so that there is no additional noise added to the very low current signal generated by the APD, thus maximising the SNR and the object detection rate of the system.


The design of the AFE board shows the


best practices to achieve the maximum signal quality, by keeping the length of the traces between the APD and the TIA as short as possible, adding vias in between the TIA inputs for maximum channel-to-channel isolation, and positioning the signal condition circuits so that they do not interfere with the other power circuits on the board. Another important feature is the ability to measure the temperature of the APD to be able to compensate for APD signal output variations due to temperature changes, as the APD’s temperature increases during normal operation. A few knobs are provided to control the offsets of the signal chain and the APD bias, which translates into APD sensitivity, to be able to maximise the ADC input range for maximum SNR. The laser board generates the optical pulses with a wavelength of 905nm. It uses four lasers that are driven simultaneously for an increase in beam strength, resulting in a longer measurement range. A PWM signal generated by the FPGA carrier board, with programmable pulse width and frequency, is used to control the lasers. The signal is generated on the FPGA as LVDS to make it less susceptible to noise as it travels from the FPGA to the laser board, through the DAQ board and the ribbon cable connecting the DAQ and the laser boards. The drive signal can be fed back to one of the ADC channels for time of flight reference. An external power supply is used to power the lasers; the design complies with International Standards IEC 60825-1:2014 and IEC 60825-1:2007 for a Class 1 laser product. Both the AFE and laser boards require optics for long distance operation. The system was proven to operate at 60m using fast axis collimators for the laser diodes that narrow the vertical FoV to one degree, while keeping the horizontal field of view unchanged, and keeping an aspherical lens for the receive side.


HDL REFERENCE DESIGN The HDL design constitutes the primary interface for the hardware, and implements all the logic to transfer data from the JESD link to the system’s memory, drives the lasers, synchronises the receiver and transmitter for accurate time of flight measurement, and implements the


/ ELECTRONICS ELECTRONICS | MARCH 2020 7


The product development cycle


communication interfaces to all the components in the hardware design. The generic architecture of the ADI’s HDL reference designs makes the framework scalable, and more accessible to port to another FPGA carrier. The design is using the Analog Devices JESD204B framework, along with several SPI and GPIO interfaces, to receive data from the AD9094 ADC and to control all of the devices on the prototyping platform.


SOFTWARE The key points that define the software stack for the LIDAR platform are ‘free’ and ‘open source’, with the “freedom to run, copy, distribute, study, change, and improve the software.” Starting from the Linux kernel and continuing with the user space tools, everything respects this.


CONCLUSION The LIDAR prototyping platform provides open-source hardware and software designs that can be referenced in the initial system architecture phases. The hardware platform and the software stack can be used through all the phases of product development - from initial system evaluation, development, and integration into the final product. The contents of the reference design, such as engineering drawings and a BOM, provide a head start in getting to a buildable, legal, and localised design system. This shortens the design cycle and likely saves money in the process, and allows customers to focus on developing the applications that bring value to their products without having to spend effort on the low level portions of the stack.


The HDL design block diagram


Analog Devices www.analog.com Tel: 01932 358530


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