FEAT RE FEA ATURE


EDA


EDA


Enabling analogue electr ica l design verification


Stev Steve Lew CadenceDesign Sy Cadence Design Systems


eve Lews Director - Custom and PCB Group Product Marketi g at vesti ates a new concept for analogue design


ewis,, Director - Custom IC and PCBGroup ProductMarketing at vestigates anew


Systems inve ew concept for analogue design


The great advantage of themethodology described here is that it takes the guesswork out of the analogue design verification flow. It becomes very obviouswhen a high-level specification ismissing links to support analogy verification tests. It is also easy to seewhen cert


rtain specifications don’t hav e


enough tests assigned to them. For example, the ISOstandardmaymandate that the part works under different environmental scenarios, or that it has certain reliability metrics built into it. If so,within the common dashboard you can open up the spec and see all of the tests that are assigned,what each of the test does, and its current status (pass, fail, pending). For designmanagers, this list of tests canmake preparing a report


ke quickwork out of rt to showthe overal l


ow


progress of the design Once the design has


been fully documented towards the finish line.


T


he emergence of a variety of ISO standards that govern automotive,


medical devices, industrial, and aviation all share one common trait: the design that you are submitting for certificationmust be traceable In the case of the standards that means each block in the designmust not only pass themandated specification


. ,


criteria, butmust also show when you tested it, which tools were used, which engineer signed off on the tests, etc. In the digital domain, standard practices have been developed over the last five to eight years that helpmanage this tracing through the


spreadsheets that require m more ad hoc,making heavy design. But on the analogue


side, it has been


anual updatin g use of


to attempt to trace what’s going on. The obvious drawback is the need formanual intervention to keep the spreadsheet updated. Each time the spreadsheet is updated by hand, errors can occur. The new Cadence Virtuoso ADE Verifier gets around this issue by being deeply integrated into the standard Virtuoso design framework so that as tests are updated, the plan is simultaneously updated.


The Virtuoso ADE Verifier is designed to allow the entry of high-lev el desig n


specifications thatmust be achieved by all the blocks in the design. Specific blocks can be identified, and proposed tests created then documented to specify what needs to occur to sign-off individual “top-down” planning flow a


llows the chip blocks. This


architect to begin by identifying the 24 24 JUNE 201 JUNE 2016 | ELEC RO ELECTRONICS CS


verification specifications “needs” first, parceling themout across the design teams to set up specific tests thatmeasure various specifications. Once the engineers create the specific tests, which can include any capability inside the Virtuoso ADE Explorer or Virtuoso ADE Assembler, the tests are linked back to the high-level specification. Simulation information is also linked back so that overall design goals can be viewed and the pass/fail/run status immediately seen. The verification tool is designed to handle significant supporting documentation that can be used to fully document the blocks, including which tests were created and why, status of simulation runs, dates, engineers, and design location.


Or, if the analogue design tasks have already been assigned through another traditionalmethod, the Virtuoso ADE Verifier can load in the tests and any results achieved, and the verification engineer can then link those results with the high-level specifications that have been identified. This process is amore familiar “bottoms-up” planning approach for analogue designers. Once the ,


Figure 1: Figure 1:


The Virtuoso ADE Verifier s designed to allow the entry of high-level design ati


specificat ons


he Virtuoso A E Verifier iis designed to allow the entry of high-level design specifications


rted, and stopped fromthis singlewindow. Post simulation, tests that are failing to meet the defined specification limits for theirmeasurements are flagged. It is quite easy to see these failures, know the exact details of the test and the enginee r


with the tool, running the simulations is very simple. Simulation jobmonitoring allow user to knowthe status of the simulation jobs. Simulation runs can be launched, sort


ows the ,


responsible, in order to quickly fix the issue so the design can continue forward.


Analogy design verification doesn’t need to be hard and you don’t need your


not be used verificationmethodo analogy engineers to


sp


achieved by all the blocks i design. Specific blocks can be identified, and proposed tests created.


achieved by sig . S


ca


entified, and proposed tests created.”


connections are in place updates are easily managed froma single cockpit.


Regression runs can be triggered for late changes, across a single group of tests or all of themat one time. These regression runs can bemade with the graphical user interface or textual regression scripts can be automatically created.


vManager too suite. So ultimatelymixed- signal verification becomes a realistic and achievable goal.


l


www.cadence.com T: 01344 360333


Cadence Design Systems www.cadence.com


entry of high-level design specifications thatmust be by all the blocks in the ific b


entry


Virtuoso ADE Veri er is designed to allowthe ry of high-level design ifica io


Virtuoso ADE Ve “The


“The Verifier designed to al ow th st b the


logies that theymay adopt digital


methodology, iliar analogy Verifier fits to. Instead, the


m E


v n


h


iding insight o the status of


d o


n f


main. The tool e analogy


ded advantage lso has the


being able to


ogy data to be dition the


dwith


al digital tools, for s Incisive


/ ELECTRONICS


ELECTRONICS


Page 1  |  Page 2  |  Page 3  |  Page 4  |  Page 5  |  Page 6  |  Page 7  |  Page 8  |  Page 9  |  Page 10  |  Page 11  |  Page 12  |  Page 13  |  Page 14  |  Page 15  |  Page 16  |  Page 17  |  Page 18  |  Page 19  |  Page 20  |  Page 21  |  Page 22  |  Page 23  |  Page 24  |  Page 25  |  Page 26  |  Page 27  |  Page 28  |  Page 29  |  Page 30  |  Page 31  |  Page 32  |  Page 33  |  Page 34  |  Page 35  |  Page 36  |  Page 37  |  Page 38  |  Page 39  |  Page 40  |  Page 41  |  Page 42  |  Page 43  |  Page 44