TEST & COMPLIANCE FEATURE
GOOD PREPARATION IS HALF THE BATTLE
COM-HPC as the upcoming new standard for modular high-end edge servers provides significantly faster and almost twice as many interfaces as COM Express. As a result, carrier board design requirements are increasing exponentially. Zeljko Loncaric, marketing engineer at congatec explores how developers can prepare for the new challenges
A
t the end of 2019, the PICMG COM- HPC technical subcommittee
approved the pinout for the new high- performance Computer-on-Module specification. Soon, the standard will be ratified officially and first modules available. System developers are already specifying their first carrier board designs and getting ready to lay out the first PCBs in preparation for the launch of their own solutions, ideally in parallel with the next embedded server processors from Intel and AMD. But the great density of high-speed interfaces on the connectors poses unprecedented challenges for carrier board developers, especially regarding signal compliance. The two 400-pin connectors provide
interfaces with extremely high clock rates of up to25Gb/s as well as PCIe Gen 4 and 5, with each of the new PCIe generations doubling the transfer rate to increase performance. While PCIe Gen 3.0 offers 8 gigatransfers per second (8GT/s), this doubles to 16GT/s for PCIe Gen 4 and then again to 32GT/s for PCIe Gen 5. Recently published preliminary details of PCIe Gen 6, however, do not indicate a change of clock frequency. But in this case, 2 instead of only 1 bit per clock will be transmitted by using 4- step pulse amplitude modulation (PAM4). Presumably, COM-HPC will also be able to support this PCIe Gen 6 technology leap since it uses an optimised version of a 56Gbps PAM4 specified connector. To put it statistically, developers are
prepared for just 12.5% (1/8 of the maximum possible bandwidth of COM- HPC) of what they will have to handle in the future. That’s a gigantic learning
curve in regard to PCIe alone. Sure, PCIe Gen 6 is still a distant concept and it will be years before the first serial products hit the market. But the current leap to the next generation is already challenging enough: Changing from PCIe 3 to 4 yields +100%, changing from USB 3.2 Gen 2 (the former USB 3.1 Gen 2 or SuperSpeed+) to USB 4.0 (40 Gb/s) +400%, and from 10 GbE to 25GbE +150% more performance. So, it’s easy to see why developers must get prepared. An important element here is early compliance testing to ensure that the final solution functions flawlessly not only during tests but also in the field. Because even if the design observes proven RF, dimensioning and layout rules for optimum signal quality, only comprehensive compliance tests can reveal critical anomalies in the application.
STATISTICALLY DISTRIBUTED AND SPORADIC ERRORS Systems that operate outside compliance, however marginally, are prone to unexpected outages. While such systems work fine much of the time, they may in practice fail in conjunction with external components. Such sporadic errors are very difficult to analyse. At the same time, they are highly critical, and experience has shown their consequences to be costly. In addition to EMC compliance tests, which ensure that set radiation levels are not exceeded, the transmitters and receivers of the high-speed communication interfaces must also meet defined signal quality standards. Let’s take PCIe interfaces as an example.
Here, compliance with the PCIe specification guarantees successful
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communication between the motherboard and any peripheral – provided both sides comply with the specification. If the values are outside, but close to the set limits, communication between board and devices can still work. However, in real use cases transmission errors may occur. And since a detected communication error triggers retransmission of the data packet, the achieved data transfer rate will drop. That a communication has successfully passed laboratory testing is no proof of compliance. This requires detailed design characterisation based on precise measurements. For this purpose, Computer-on-
Module specialists such as congatec have built their own test labs, equipped with expensive high-precision test equipment. The advantage of an in- house lab is obvious: The deeper you work in the safe zone, the higher the reliability and functionality in the long term. Knowledge of the precise safety margins facilitates quality assurance as well as quality improvement. The first step is to optimise products with the aid of simulation. However, verifying the optimisations requires extensive receiver (RX) and transmitter (TX) compliance measurements. To be able to future- proof high-speed interfaces such as those offered by COM-HPC, congatec installed a new test station back in 2018 for the characterisation of the next generation of transmitters and receivers – including PCIe Gen 5.0, USB 4.0, and far beyond.
congatec AG
www.congatec.com
ELECTRONICS | JULY/AUGUST 2020 19
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