POWER DEVICES
Optimising the gate drive of SiC MOSFETs
Didier Balocco, business marketing engineer at Onsemi discusses the features of SiC MOSFET devices and the demands they place on their gate drive circuitry and an IC that can address these and other system-level considerations
S
ilicon carbide (or SiC) MOSFETs have distinct advantages over traditional silicon MOSFETs and IGBTs in high voltage switching power applications, high frequency (hundreds of kilohertz) switching is possible using silicon MOSFETs, but they cannot be used at very high voltages (>1000V). Conversely, while IGBTs can be used at high voltages, their “tailing current” and slow turn-off means they are limited to lower frequency switching applications. SiC MOSFETs offer the best of both worlds - high-frequency switching at high voltages. However, the unique device characteristics of SiC MOSFETs mean they place particular requirements on gate driver circuitry. Understanding these characteristics allows designers to select gate drivers that can improve device reliability and overall switching performance.
SiC MOSFET characteristics By comparison with silicon devices, SiC MOSFETs have lower transconductance (gain), higher internal gate resistance, and their gate turn−on threshold can be less than 2V. As a result, the gate must be pulled below ground (typically −5V) during the off−state. SiC devices generally require a gate−source voltage between 18V < VGS < 20V to lower on-resistance (RDS) during the on-state. Operating a SiC MOSFET at low VGS can result in thermal stress or possible failure due to high RDS. Other effects associated with the low gain can directly impact several important dynamic switching characteristics, which must be considered when designing an adequate gate−drive circuit. These effects include on−resistance, gate charge (Miller plateau), and over−current (DESAT) protection.
On-Resistance
At low VGS, the on−resistance versus junction temperature characteristic of some SiC devices can appear to be parabolic* (due to a combination of internal device features). (*This applies to onsemi M1 and M2 SiC MOSFETs.) When VGS = 14V, RDS appears to
Figure 2: On−resistance vs. Junction temperature for a M3 SiC MOSFET
Gate charge
When a gate voltage (VGS) is applied to a SiC MOSFET, the charge is transferred to increase the gate voltage from VGS(MIN) (VEE) and
26 DECEMBER/JANUARY 2023 | ELECTRONICS TODAY
have a negative temperature coeffi cient (NTC) characteristic where the resistance decreases with increasing temperature. This feature of a SiC MOSFET is directly attributed to its low gain, meaning that If two or more SiC MOSFETs were placed in parallel while operating with low VGS (negative TC), the result could be catastrophic. Therefore, parallel operation between SiC MOSFETs is only recommended when VGS is suffi cient to ensure reliable positive TC operation (i.e. VGS > 18V).
Didier Balocco
VGS(MAX) (VDD) as quickly as possible. Since the internal capacitances of the device are non− linear, a VGS versus gate charge (QG) curve can be used to identify how much charge must be delivered for a given VGS. This ‘Miller plateau’ for a SiC MOSFET occurs at higher VGS and is not fl at as for a silicon MOSFET. A non−fl at Miller plateau implies that VGS is not constant over the corresponding range of charge, QG, which is another consequence of the low device gain. It is also notable that QG = 0 nC (the amount of charge needed to turn off a SiC MOSFET) does not occur at VGS = 0 V, so VGS must be pulled below ground (−5 V in this case) to fully discharge the gate.
Figure 1: On−resistance vs. Junction temperature for a M1 or M2 SiC MOSFET
The new M3 SiC generation shows a positive temperature coeffi cient for all VGS and for the full temperature operating range
As we want to measure the amount of charge needed to turn-on or -off the SiC MOSFET, we use curve plots only with an Qg increment (or Qg accumulation or Qg variation). The value is also called Qg. It can be confusing. This graph has to be interpreted as the amount of energy needed and not has an absolute energy stored in the gate-to-source capacitor.
Figure 3: Gate−Source voltage vs. Gate charge for a SiC MOSFET
The main reason to use negative gate drive blocking voltage is to reduce drain current leakage during off state. This is also due to the low transconductance gain. Using negative blocking voltage also reduces the switching losses, mainly during turn off.
Therefore, almost for all SiC MOSFETs, it is recommended to use a minimum VGS of −5 V < VGS(MIN) < −2V during off state, with some
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