Data acquisition
and outputs to a file, the frame mapping of the mode in table format.
DEBUGGING THE JESD204B/JESD204C INTERFACE
In addition to debug register fields and test modes available in ADI’s high speed data converters, each protocol layer IP block has features that can be enabled to help with debugging a the JESD204B/JESD204C interface once it is implemented within a system.
PHY Layer Debug
The physical interface between high speed data converters and FPGAs has high speed signals, with fast rising and falling edges moving across parallel lanes on a board. While debugging a JESD204B/JESD204C link, there are two recommended debug points for the PHY layer.
Serialiser Deserialiser Clocking A phase-locked loop (PLL) synthesiser produces the high speed clock that drives the serial transmitter and receiver path on both the FPGA and high speed data converters. The PLL is a crucial block of the clock data recovery (CDR) circuit and is usually driven by a reference clock that has a defined relationship with the line rate. The ADI data converters and the FPGA IP both have the provision to check for PLL lock. In cases where this reference clock isn’t set to the correct rate, the PLL will be unlocked.
Pseudo Random Binary Sequence (PRBS) Patterns
PRBS patterns can be used to test how the high speed parallel lanes moving data between the data converter and the FPGA affect all possible data patterns. In addition, they are a valuable tool for testing the signal integrity of the physical interface. ADI’s ADC, DAC, and MxFE family of products supports PRBS modes (PRBS7, PRBS15, and PRBS31) that can be run at the maximum rate supported by the product.
The FPGA transceiver PHY IP options for FPGAs from AMD Xilinx and Intel also have built-in PRBS modes. In addition, they also have standalone signal integrity IP blocks (Xilinx iBERT) that can be used. The IPs also have pre-emphasis, post- emphasis, and voltage swing settings that can be adjusted to offset some signal integrity issues.
DATA LINK LAYER DEBUG
The process of the JESD204B/JESD204C link establishment involves a synchronisation sequence which, if not completed correctly, will lead to a failure in the link being established. For JESD204B use cases or designs, code group synchronisation (CGS), initial lane synchronisation (ILAS), and the physical sync signal must be monitored to ensure the link is established. In the case of JESD204C, it is the sample header (SH) lock and the extended multiblock (EMB) lock. There are two recommended debug points for the data link layer.
JESD204B/JESD204C Mode Mismatch Since the selected mode (L, M, F, S, K, and other parameters) determines how the link layer encodes
Instrumentation Monthly March 2024
Figure 3. An ADS9v2 FPGA platform and its components.
and decodes the data sent over the interface, the FPGA and the data converters need to be set up in the same mode. In cases where there are inconsistencies in data that are not coming from the physical link, it is helpful to verify that the JESD204B/ JESD204C parameters are set up correctly.
JESD204B/JESD204C Lane Mapping Mismatch Routing the high speed physical parallel lanes between the data converter and the FPGA can be challenging. A crossbar that allows routing physical lanes to logical lanes on a receiver and logical to physical lanes on a transmitter can be used to ease the restrictions on routing. If a lane mapping crossbar is used the link not being established could result from a lane mapping mismatch, and confirming mapping could be a practical debug step.
Transport Layer Debug
The transport layer is responsible for translating between lane data and sample data. In a case where there are inconsistencies in the data output from the transport layer, there is one recommended debug approach.
Pattern Mode ADI’s ADCs have built-in test modes that can generate a few different kinds of predefined digital patterns and user-defined patterns. These patterns are easier to interpret on the output and, therefore, well-suited for detecting errors in the FPGA receive transport layer.
In the case where the FPGA transmit transport layer is responsible for generating the correct lane data from sample data using a known pattern as its input can prove helpful as a debug step as well.
65 Error Monitoring
In addition to link establishment, the high speed data converters and the FPGA IP modules can report any errors on the link while the data is being transmitted or received. This knowledge is beneficial for link monitoring and provides an additional level of system debugging.
CONCLUSION
As the next generation of wideband RF transmitters and receivers evolves to meet ever- increasing sample rate and throughput demands, ADI’s high speed ADC, DAC, and MxFE family of products enabled by the JESD204B/JESD204C interface running at speeds up to 32.75Gbps remains an integral part of the solution. With a wealth of design resources readily available such as FPGA reference designs, FPGA IP modules, cutting-edge tools, and support, designers can save significant development time and seamlessly upgrade to a high speed data converter with the JESD204B/JESD204C interface.
Analog Devices
www.analog.com
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