Data acquisition
UNLOCK HIGHER DATA TRANSFER SPEEDS BY UPGRADING TO THE JESD204B/JESD204C INTERFACE
INTERFACING WITH HIGH SPEED DATA CONVERTERS
As data converters continue to support faster sample rates and higher resolutions, signal integrity concerns at higher data transfer speeds mean traditional input/output (I/O) technologies are unable to meet today’s bandwidth requirements. Furthermore, high speed data converters have increasingly taken on more of the system workload by incorporating power-optimised digital signal processing (DSP) engines. The receive path includes highly configurable digital downconverters (DDCs), programmable finite impulse response (FIR) filters, and automatic gain control (AGC). The transmit path features digital upconverters (DUCs), programmable delays, and transmit digital predistortion (DPD) support. This functionality can be offloaded from the FPGA or the ASIC to the converter. This results in a higher bandwidth system and a great SWaP (size, weight, and power).
The JESD204B and JESD204C standards are designed to meet the demands of next- generation data converter applications. They leverage high bandwidth serialiser/ deserialiser (SerDes) based interfaces along with protocol-level encoding, scrambling, and synchronisation techniques to enable transfer rates up to 32.5Gbps with a reduced number of differential interconnects. Figure 1 shows a typical high speed converter
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to FPGA interface, such as the one on the latest addition to Analog Devices’ MxFE family of products that can support a maximum of 24 JESD204C differential parallel lanes each for transmit and receive, each capable of moving data at a maximum of 32.5Gbps for a net throughput of almost 800Gbps simultaneously in each direction.
IMPLEMENTING THE JESD204B/ JESD204C INTERFACE ON AN FPGA The flow of data over the interface between the ADC, DAC, or MxFE to an FPGA is governed by the JESD204B or JESD204C standards. For JESD204B, the transmitter in the system assembles parallel data into frames and uses 8-bit/10-bit encoding and optional scrambling to form serial output data. The initial link establishment requires special control characters to be sent and received for synchronisation. Additional control characters are embedded in the data stream to maintain synchronisation. While the JESD204B protocol lane rates are limited to 16Gbps, the JESD204C protocol supports lane rates up to 32.75Gbps. JESD204C uses a 64-bit/66-bit encoding scheme that provides a much higher encoding efficiency and uses an entirely feed-forward synchronisation process, eliminating the need for a handshaking process for initial link synchronisation. Figure 2 shows the data path that can be broadly split into four layers, with each layer performing specific tasks within a design.
JESD204B/JESD204C FPGA IP To help accelerate the development of a system that requires interfacing with high speed data converter products with JESD204B/JESD204C, there is FPGA IP from ADI as well as FPGA vendors for each layer in the data path. While the eventual selection will depend on the software/hardware decisions relevant to the system, the FPGA IP modules are built to be flexible enough to allow a mix-and-match approach to arrive at the best possible solution.
1. PHY Layer
The physical layer (PHY layer) enables the movement of protocol frames at the specified line rate using the SerDes. It includes transmit drivers, receiver equalisers, and clock and data recovery circuits.
The physical layer often requires hardened transceiver IP and is FPGA device dependent. Therefore, the FPGA manufacturer and the FPGA product family determine what can be used. The AMD Xilinx high speed serial transceivers (GTX, GTH, GTY, GTY-P series) and Intel transceiver phy (L-Tile, H-Tile, E-Tile series) are options available on their FPGA devices. The transceivers become an essential metric in deciding if an FPGA device is suitable for the end applications, since they are rated for different maximum values.
2. Data Link Layer
The data link layer takes care of 8-bit/10-bit or 64-bit/66-bit encoding/decoding based on the
March 2024 Instrumentation Monthly
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