Data acquisition


In this article, Nikhil Ahuja, product applications engineer at Analog Devices, provides an overview of the JESD204B/JESD204C interface on the ultrawideband direct RF sampling high speed data converters and how to implement these interfaces to enable higher data transfer speeds. The article explains how high speed data converters with the JESD204B/JESD204C interface add value to the end system application. It describes the role of each implementation layer and highlights FPGA IP, tools, and platform solutions to enable a seamless upgrade as well as an optimal approach to debugging once an interface has been implemented.


Figure 1. Interfacing with high speed data converters.


protocol selection, descrambles, lane aligns, and defames lane data. For JESD204B, it performs frame alignment character replacement. For JESD204C, it performs multiblock and extended multiblock alignment required to synchronise data over the link. The ADI JESD204B/JESD204C transmit link layer and ADI JESD204B/JESD204C receive link


Instrumentation Monthly March 2024


layer IPs are optimised for interoperability with ADI high speed data converter products and unencrypted RTL and IP drivers are available to use in FPGA designs to interface with ADI high speed data converter products. For the data link layer, the AMD Xilinx FPGA JESD204 or Intel FPGA JESD204 framer and de-framer IPs can also be used.


3. Transport Layer


The transport layer converts lane data back to ADC sample data on the transmit path or DAC pattern data into lane data on the receive path. The configuration determines the sample data format.


The ADI ADC companion transport layer RTL generator and the ADI DAC companion


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