Data acquisition
In general, the overall system complexity and cost increase, scaling up with the system size, especially compared to SAR ADCs where this problem was solved more easily by just aligning the conversion start to the Global_SYNC signal. In addition, in many cases the use of a sigma-delta ADC must be not possible as per the system restrictions and limitations explained earlier in the article.
EASILY RESYNCHRONISE SIGMA-DELTA ADCS WITH NO DATA DISRUPTION The AD7770 family (which includes AD7770, AD7771, and AD7779) has a built-in SRC. With the introduction of this novel architecture, the restriction of the decimation factor (N) being a fixed value is no longer valid. The SRC allows you to program decimal
numbers, not only integers, as the decimation rate (N), which allows you to program any desired output data rate. On the previous synchronisation method, as N was fixed, the external clock needed to change to
adjust fMOD in order to perform the synchronisation routine. Using AD7770 family of products, as the N
is flexibly programmable and reprogrammable on-the-fly, any ODR can be programmed
without having to change fMOD and without data disruption. This novel method for resynchronising sigma-delta-based subsystems, making use of the SRC simplifies the resynchronisation, minimising the complexities described in the previous sections.
The new method is as follows:
When the Global_SYNC signal is received, each subsystem checks if it is sampling synchronously or not, taking the data ready signal as a reference and using the group delay to find the actual sampling instant.
If there is a discrepancy between the sampling instant and when the Global_SYNC signal has been received, the local controller quantifies
the time difference (tahead or tdelayed) as shown in Figure 9.
A new ODR is programmed to temporarily generate a faster or slower ODR through modifying the decimation factor (N) by means of the SRC. The whole operation of resynchronisation will always take 4 samples (or 6 if the sinc5 filter is enabled on AD7771), but without interrupting the data flow due to these samples which are still valid and 100 per cent settled.
Once the required amount of DRDY has been received, the decimation factor is reprogrammed again to return to the desired ODR, which guarantees that the sigma-delta converter is synchronised with the rest of subsystems, as shown in Figure 11, with no data flow disruption.
Instrumentation Monthly September 2020 Figure 10. Synchronisation method using PLL to tune the modulator frequency.
Figure 9. Quantifying the discrepancy from each ADC’s sampling instant (provided the group delay is known) to the global synchronisation signal.
Figure 11. The sample rate converter adjusts the ODR on the fly in order to resynchronise the sampling on all devices.
CONCLUSIONS Critical distributed systems require synchronous conversion in all the subsystems and a continuous data flow. SAR converters provide an intuitive way to resynchronise the sampling by readjusting and aligning the conversion start signal with the Global_SYNC pulse.
In applications that require high dynamic
range (DR) or signal-to-noise ratio (SNR) specifications, SAR is not an option, but traditional sigma-delta converters become a challenge to use due to their inflexibility to readjust without disrupting the data flow. As seen in the example, the SRC provides a seamless synchronisation routine with minimum latency and much lower cost and complexity than other solutions.
There are plenty of applications where the SRC can also be advantageous. As with the power line monitoring example, any line frequency change can be compensated for by immediately changing the decimation rate on the fly. That way, the power line is always sampled at a coherent sampling frequency. Here, in critical distributed systems, it is demonstrated that the SRC can also be very useful for resynchronising the system without having to interrupt the data flow and with no need for extra components like PLLs. The AD7770 solves the traditional problem of synchronising sigma-delta ADC- based distributed systems, without missing samples and avoiding the added cost and complexity of the PLL-based method.
Analog Devices
www.analog.com 27
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