Data acquisition
NYQUIST AND OVERSAMPLING ADCS Before moving into explaining how to synchronise the sampling instant of many ADCs, it is good to understand how each ADC topology determines when to sample the analogue input signal, and the benefits and drawbacks of each architecture.
Nyquist or SAR ADC: This converter’s maximum input frequency is dictated by Nyquist, or half-sampling frequency.
Oversampling or sigma-delta ADC: The maximum input frequency is typically a fraction of the maximum sampling frequency, typically around 0.3×.
On one hand, the SAR ADC’s input signal sampling instant is controlled through an external pulse applied to the conversion start pin. If a common conversion start signal is applied to every SAR ADC in the system being synchronised, as shown in Figure 2, they will all trigger the sampling simultaneously on the conversion start signal’s edge. By just making sure there are no significant delays between the signals—that is, the conversion start pulses reach every SAR ADC at the same moment in time—the system synchronisation can easily be achieved. Note the propagation delay between the pulse reaching the conversion start pin and the actual sampling instant should not vary from device to device, and it is not significant in precision ADCs where the sampling speed is relatively low. Sometime after the conversion start pulse is
applied, which is called conversion time, the conversion result will be available through the digital interface in all ADCs. On the other hand, sigma-delta ADC operation
is slightly different due to its architecture. In this type of converter, the internal core—the modulator— samples the input signal at a much
higher frequency (modulator frequency, fMOD) than the minimum frequency dictated by Nyquist, which is the reason why it is called an oversampling ADC. By sampling at much higher frequency than
strictly needed, an extra number of samples are gathered. All the ADC data is then postprocessed through an average filter for two reasons:
The noise decreases 1 bit for every four averaged samples.
An average filter transfer function is a low- pass filter. As the sigma-delta architecture pushes its quantisation noise toward high frequencies, this shall be removed, as shown in Figure 3. So, this filtering is accomplished by this averaging filter.
The number of samples averaged, known as the decimation ratio (N), dictates the output data rate (ODR) that is the rate at which the ADC provides the conversion results, in samples per second, as indicated in Equation 1. The decimation ratio is typically an integer number with a set of predefined values discretely programmable (that is
Instrumentation Monthly September 2020
Figure 3 (above). Sigma-delta noise shaping.
Figure 4 (above). Sigma-delta ADC flow.
Figure 5 (above). Sigma-delta system reset synchronisation. N = 32, 64, 128, etc.) on the digital filter. So, by
keeping fMOD constant, the ODR will be configured depending on the value of N, within the set of predefined values.
The averaging process is typically implemented
internally by a sinc filter, and the analogous conversion start pulse for the modulator is generated internally as well, so there is no external control on triggering the conversion process. This type of converter is indeed continuously sampling, tracking the input signal, and processing the data acquired. Once the process (sampling and averaging) is completed, the converter generates a data ready signal to indicate to the controller that the data can be read back through the digital interface. As shown in Figure 4, the flow for a sigma-delta can be summarised in four major steps,
The modulator samples the signal at fMOD frequency.
The samples are averaged through the sinc digital filter.
The result from the sinc filter is offset and gain corrected.
The data ready pin toggles, indicating that the conversion result is ready to be readback by the controller.
As there is no external control on when the
internal sampling triggers, in order to synchronise multiple sigma-delta ADCs within the distributed system, all the digital filters must be reset simultaneously as it is the digital filter that controls the start of the averaged conversion. Figure 5 shows the effect on the
synchronisation assuming same ODR, and fMOD in all the sigma-delta ADCs. Similar to the SAR ADC-based system, it must be ensured here that the reset filter pulse reaches all subsystems at the same time. However, note that every time the digital filter
is reset, the data flow is interrupted as the filter must settle again. The duration of the data disruption in this case depends on the digital
filter order, the fMOD, and the decimation rate. An example is shown in Figure 6 where the LPF nature of the filter delays the time until a valid output is generated.
IMPLICATION ON SYNCHRONISING THE SAMPLING IN DISTRIBUTED SYSTEMS In a distributed system, the global synchronisation signal (let us call it Global_SYNC) is shared across all the modules/subsystems. This synchronisation signal could be generated by the master or by a third-party system, like the GPS 1 pps, as shown in Figure 1. Once the Global_SYNC signal is received, each module must resynchronise the instantaneous sampling of each converter, and most probably its
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