Data acquisition
The controller calculates the time difference between the sampling instant (calculated backwards from the data ready signal by knowing the group delay, as shown in Figure 8) and the Global_SYNC pulse. The group delay is a data sheet specification that accounts for the time between when the input is sampled until the data ready pin toggles, indicating that the sample is ready to be read.
If there is a discrepancy between the sampling instant and Global_SYNC, the local controller
Figure 6 (above). Data disruption due to digital filter settling time.
quantifies the time difference (tahead or tdelayed), as shown in Figure 9.
If there is a discrepancy, the sigma-delta filter could be reset or the fMOD could be modified in order to adjust the sigma-delta sampling during a
few samples. In both cases, a few samples would be missed. Note that by changing the local clock
frequency (fMOD), the sigma-delta ADC is modifying its output data rate (ODR = fMOD/N), such that the ADC samples its analog input either
slower or faster, with the intention for this ADC to catch up the rest of the ADCs on the system and with the Global_SYNC.
Figure 7(above). Aligning the SAR ADC conversion process to a global synchronisation signal.
local clock, to guarantee simultaneity. In a SAR ADC-based distributed system, the resynchronisation is intrinsically easy as described in the previous section: the local clock (which manages the conversion start signal) realigns with the Global_SYNC signal, getting these signals in synchrony from then on. This has an implication in terms of generating frequency spurs because, during the synchronisation, there is one sample that has been gathered at different time and distance, as highlighted in blue in Figure 7. In distributed applications these spurs may be acceptable, while disrupting the data flow would have been indeed critical in applications like the power line monitoring mentioned earlier, for instance. In sigma-delta-based distributed systems, the resynchronisation with regards to a Global_SYNC signal is a little bit more complicated because the modulator is continuously sampling the analogue input signal, and the conversion process is not externally controlled as it is in an SAR ADC. The easiest way to synchronise multiple sigma- delta-based distributed systems is by resetting the
digital filter: all modulator samples gathered and stored to be used on the average filter are dumped, and the digital filter is emptied. That means it will take some time, depending on the digital filter order, to settle its output again, as shown in Figure 5 and Figure 6. Once the digital filter is settled, it will provide valid conversion data again, but resetting the digital filter on sigma-delta ADC implied data disruption may not be acceptable considering the amount of time the settling takes. The more often the distributed system needs to be resynchronised, the more data flow interruptions there will be, which can make sigma-delta ADCs impractical for critical distributed systems due to the continuous data flow disruption. Traditionally, a method to minimise the data
disruption has been the use of a tunable clock, like a PLL that decreases the error between the global
sync and the fMOD frequencies. Once the Global_SYNC pulse is received, the
uncertainty between the sigma-delta ADC conversion start and the Global_SYNC pulse can be calculated following a process similar to:
If the fMOD is updated, once in synchrony, the master clock frequency is reverted back to original
frequency to return to previous ODR, while the subsystem becomes synchronous from then on.
This process of changing fMOD during a certain
period of time is shown in Figure 10. This method may not be appropriated in some cases as there are a couple of details to consider:
Changing the modulator frequency to non-multiple values may be unpractical.
If fine frequency tuning is possible, the frequency steps while changing must be small, otherwise the digital filter may go out of bounds, so the lead time for the synchronisation routine becomes longer.
If the ODR change needed is big enough, it could be solved by changing the decimation rate (N) instead
of the modulator frequency (fMOD), but this would also imply missing samples.
Using a PLL implies an extra amount of power being consumed plus its own settling time until reaching the desired modulator frequency.
Figure 8. Time delay between the analogue input being sampled and the data ready toggling. 26
September 2020 Instrumentation Monthly
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