electronica 2014 INDUSTRIAL ELECTRONICS Hall A4 Stand 538
Avoiding the limitations of the l2C standard
Chris Gobok looks at how to resolve common I2C issues I
2C is a popular digital interface used for short- range chip-to-chip communication that features a simple 2-wire bus, ease of implementation, and up to 400kHz operation in fast mode. However, like any other standard, issues can arise when an application pushes the
compatibility with older non-compliant or unknown I2C devices, busses mysteriously stuck low, or simply not having enough device addresses available are all challenges I2C designers are fairly familiar with, but don't always have easy answers to.
original I2C specification to its limit or simply when the specification falls short in addressing today's system requirements. As systems become more complex, more I2C devices are added to the bus and may start to compromise certain parameters.
The most common issues I2C system designers face today are of electrical, timing or signalling nature. Increasing system size without exceeding the 400pF bus capacitance limit,
Heavy electrical demands met The I2C standard specifies that the maximum bus capacitance cannot exceed 400pF. However, traces, long cables, and devices all possess and add capacitance to the bus, which makes it especially difficult for large systems to sometimes stay under the defined 400pF limit. Another common issue is I2C devices with different supply voltages can't be mixed and matched on the same bus. Some systems also require inserting and removing I/O boards from a live backplane, and without the proper precautions this can corrupt the backplane. Failure to address any of these electrical issues may compromise the I2C compliance, data integrity, or reliability of your system. Thankfully, I2C bus buffers have resolved these basic issues, providing busses with capacitive buffering, level shifting, and hot swapping capabilities by precharging the lines. As systems continue to grow, new electrical issues arise and it has become more apparent that the benefits provided by earlier bus buffers have come at the expense of compromising certain I2C specifications. Bus buffers require a scheme to differentiate an externally driven logic low from their own driven low, which have resulted in buffers that either drive output logic lows (VOL) above the 0.4V I2C specification or buffers that drive a VOL with an offset. As more of these older buffers are added to the bus, logic low noise margin is compressed further, increasing the bus' susceptibility to noise. Larger systems benefit greatly from a near- ideal bus buffer that restores logic-low noise margin to the I2C specification, namely, a fast buffer that is active until the bus voltages crosses the input logic-low (VIL) value of 0.3VCC and does not load the bus. An additional requirement in large systems is backward compatibility with buffer products whose rise time accelerators (RTAs) turn on below 0.3VCC or with products that drive a noncompliant VOL of 0.6V. Linear Technology's LTC4315 is a new bus
Figure 1 10 CIE electronica 2014
buffer that addresses all of the issues mentioned so far. It does the usual breaking of large bus capacitances into smaller <400pF segments,
level translates bus supplies ranging from 1.4V to 5.5V, and provides hot swap capabilities so I/O cards can be safely inserted/removed from a backplane. Perhaps more importantly, it guarantees a high VIL of 0.3Vcc, ensuring a high logic-low noise margin at all times. As a result, multiple LTC4315s can be cascaded without worry of compressing noise margins, perfect for large or noisy systems. The LTC4315 is also interoperable with devices that drive a high VOL > 0.4V and with products whose RTAs turn on at voltages below 0.3VCC, so you can build a system without having to know or worry about what types of I2C will eventually connect to your system.
Bad timing avoided There are two major timing issues that are prevalent in I2C systems. First, I2C signal rise times are generally dictated by the bus pull-up resistors, which are sometimes inadequate if a faster slewing bus is desired, such as the case in PICMG specifications which call for both the SCL and SDA signals to rise from 1V to 2.3V in 900ns with a 2.7k pull-up to 3.3V and a 690pF load. Otherwise, high bus capacitance and limited pull-up current can critically lengthen rise times to the point of violating the max rise time I2C specification of 1µs at 100kHz or 300ns at 400kHz. Linear Technology offers many bus buffers with selectable rise time acceleration, like the LTC4315, as well as stand-alone dedicated rise time accelerators. These autonomous rise time accelerators provide strong, slew-limited, pull-up currents so that rise time requirements are met. The accelerators are automatically activated only during positive bus transitions and make the bus
Figure 2
voltages rise at a particular rate, which improves both board and system reliability by providing smooth, controlled transitions during rising edges. Systems also become much less susceptible to noise on rising edges since the accelerator pull-ups present impedances
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