Materials Case Study
to make strong commitments: The semiconductor manufacturer must be prepared to build a long-term relationship with both tool builder and chemistry supplier; in turn, they must commit resources to see the new surface preparation solution to a successful launch. Under the old model, a development
process that took 70 weeks, with 100-300 additional pilot wafer runs and testing, would have been replaced with a process that hypothetically should have taken 40 weeks or less to reach full ramp. By saving time, it might have been possible to eliminate 25-30 percent in additional development costs for the tool builder, the chemistry supplier and the manufacturer, by refining cleaning processes and tooling and chemical formulation characteristics as a single effort.
Another example is that of implementing a
new process for post-ash residue removal in vias in a new node or new geometry. In this hypothetical example, the semiconductor manufacturer establishes pre-conditions that limit the best technological solution: They may specify an immersion tool or a single wafer spray tool, due to familiarity with the system and a perception that it is a lower cost solution overall.
The manufacturer may also set a maximum unit cost for the wet tool chemistry — $30/gallon, for example.
This immediately limits the chemistry supplier’s technology choices; the manufacturer may even specify an “in-house” formulation of commodity chemistries, rather than opening the door to the chemical company’s engineered options. A standard rule of thumb is that wet
processes have lower indirect and direct costs per wafer, compared to dry process tools. However, chemistries designed for bath tools do not directly transfer to spray tools or other tools using novel delivery methods. If the semiconductor manufacturer directs the tool builder to utilize a single wafer spray tool (possibly by modifying a toolset already in use at the manufacturer’s fab) then the chemistry used in that tool must be optimized to that toolset. All the risks rest squarely with the chemistry supplier: They must optimize the performance of their chemistry with the decision to use a single wafer tool — and at a price point that may force the use of a less effective chemistry for that tool. Development costs could increase, due to additional fine-tuning of process variables to minimize impact on vias and substrates, or more
frequent bath changes, or increasing material and waste treatment costs. Costs could also increase for the chip manufacturer as it may need to unexpectedly retrofit its cleaning tools to be compatible with these new chemistries.
Collaborative Solutions
In a collaborative model, the tool builder and chemistry supplier will get a detailed understanding from the semiconductor manufacturer of the total yield and process goals, on a per-wafer-pass basis, for the post- etch residue removal process; then together they develop the solution, which might (or might not) match the manufacturer’s original tooling and chemistry assumptions. The chemistry supplier could propose an
engineered chemistry that works in a particular type of tool — a wet bench immersion tool, for example - that has a bath life three times longer than the chemistry used in a spray tool, and generates similar or even better yields. The tooling is different, and the chemistry unit price is higher than what the manufacturer originally assumed; but since the chemistry has a longer life and the tool uses it much more efficiently, total process cost can be shown to be lower. This approach will not only help chemistry suppliers — tool builders have an equal potential to benefit. They won’t be forced to re- design tools with materials of construction that are incompatible with new chemistries, or have insufficient capabilities for broad temperature settings, flow rates and mixing features. Given the full scope of the challenge, the chemistry supplier and tool builder could propose the optimum solution based on process times, and tool, materials and ancillary costs (waste
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Semiconductor manufacturing requires intense material know how
www.euroasiasemiconductor.com Issue III 2011
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