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Interconnect Bonding


The key to low temperature


bonding for 3D integration Pressure and temperature are key requirements in the interconnect bonding process for low resistance, high yielding and reliable interconnects. Jason D. Reed, Matthew Lueck, Chris Gregory, Alan Huffman, John M. Lannon, Jr. and Dorota S. Temple, Centre for Materials and Electronic Technologies, RTI International discuss results of bond and stress testing of Cu/Sn-Cu bonded dice and Cu-Cu thermocompression bonded dice in large area arrays and show that in the case of Cu/Sn-Cu, the use of a mechanical key was found to improve yield.


power consumption and enhanced functionality of microsystems. Heterogeneous technologies such as sensors, imaging arrays and others can be implemented in their optimal process flows and then integrated using the high density interconnects. Several research groups have presented work in the area of metal-metal interconnects [1-4]. In this paper we review the status of the development of high yield bonding at 10µm pitch, highlighting the use of a mechanical key to prevent misalignment and slippage during thermocompression. These results represent an order of magnitude increase in density (106 interconnects per square centimeter) as compared with the state-of-the- art in traditional flip-chip bonding.


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Design and Fabrication Three test vehicle devices were fabricated based on the following approaches:  Cu/Sn - Cu bond with no mechanical key.  Cu/Sn - Cu bonding with a mechanical key on one of the dice to prevent misalignment and slippage during bonding. The keys also prevent Sn from bridging acrossbonds, an issue noted in previous work [5].


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igh density interconnects enable further miniaturization, reduced


 Cu - Cu thermocompression bonding with chemically-mechanically polished (CMP’d) Cu bond pad surfaces and with CMP’d Cu to as- plated Cu bond pad surfaces. The as-plated Cu pads also had a mechanical key.


These approaches were designed to be compatible with post-CMOS processing on 200mm wafers. To test these bonding approaches, RTI fabricated test vehicles containing 512 x 640 area arrays of bond pads with 10µm pitch on 200mm diameter wafers. Each test vehicle provided 256 daisy chain channels, with 1272 individual chip-to-chip bonds per channel, giving good spatial resolution of potential defects.


Fig. 1. (left) SEM of top die pillar after tin plating, (above right) SEM of the top die 10_m pitch array, (below right) scaled drawing of Cu/Sn pillars (3.5um copper and 2.5um tin)


www.euroasiasemiconductor.com  Issue III 2011


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