Feature: Software & Tools
The MxFE series and AD917x RFDAC devices from Analog Devices all contain on-chip integer-type PLL synthesizers to generate DAC and ADC sampling clocks
Ten select Phase Noise Table and properties from the top menu; see Figure 20.
Te model should then be available in the library for selection when creating a new design.
Figure. 20 Reference Phase Noise Table select
Select Change Number of Rows. Ten change the number to match the measured phase data number of points and press OK; see Figure 21.
Measured vs. modelled simulation To determine the accuracy of the ADIsimPLL model data with measured results, the AD9081-EBZ evaluation platform was configured to generate a DAC output at 3GHz using an fDAC = 1GHz. Te plots in Figures 23 and 24 show measured phase noise (in blue) vs. ADIsimPLL model phase noise (in red) for the default charge pump current (ICP) = 2mA and the maximum ICP = 6.4mA.
Figure 23. The AD9081 phase noise, fDAC = 12GHz, DAC output = 3GHz, ICP = 2.0mA
Figure 21. Reference Phase Noise Table properties
Ten enter the measured phase noise data of the reference to the table. Te first entry of each pair is assumed to be the offset frequency, and the second the phase noise at that frequency; see Figure 22. Te offset frequency entries must increase.
Figure 24. The AD9081 phase noise, fDAC = 12GHz, DAC output = 3GHz, ICP = 6.4mA
Figure 22. Reference Phase Noise Table data entry
Press Save on the top leſt and save within the reference folder. See Figure 16.
Te current version of ADIsimPLL includes models for the MxFE and the AD917x RFDAC. As it can be seen here, the performance results provided by the MxFE models match closely to actual bench measurements making this modelling tool a very useful and worthwhile process to use prior to schematic entry.
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