Feature: Software & Tools


application, the phase noise/integrated jitter performance of the on-chip PLL/VCO synthesizer, locked to the input reference, can be sufficient to meet the application requirements; however, in some cases an external clock source with lower phase noise may be needed, instead of the on-chip PLL/VCO. Te decision of what clock to choose can be simplified with the ADIsimPLL soſtware, which models the desired integrated PLL/VCO, as well as the reference, for best phase noise/jitter performance. Modelling the reference source allows the designer to quickly determine the effect of reference noise on the sampling clock, which eases the selection process of the reference clock. ADIsimPLL can also be used for modelling the on-chip charge


pump current and external loop filter components, to determine their optimum values.


Software for the design of mixed-signal front-end and RF DAC sampling clocks


By Brigid Duggan,


product applications engineer, Analog Devices


C


lock generation is important for the functioning of many electronic circuits and systems, so choosing the right components will deliver their best performance. Digital-to-analogue converters (DACs) and analogue-to-digital converters (ADCs) use clock information for sampling. Here, most


important criteria are phase jitter and phase noise floor, which impact the signal-to-noise ratio (SNR). Te MxFE series and AD917x RFDAC devices from Analog


Devices all contain on-chip integer-type PLL synthesizers to generate DAC and ADC sampling clocks. Depending on the


24 September 2024 www.electronicsworld.co.uk Figure 2. Starting a new design in ADIsimPLL


MxFE sampling clock design example In this article we will use the example of an input reference frequency of 500MHz to design a PLL with a VCO frequency of 12GHz, with the help of the ADIsimPLL soſtware. To create the MxFE sampling clock design, you can download


the ADIsimPLL design tool from analog.com/ADIsimPLL. Once installed, to begin the design process, open ADIsimPLL; see Figure 1.


Figure 1. The ADIsimPLL welcome screen Close the tutorial; see Figure 2.


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