Feature: Software & Tools


Select Create a New Design, then click OK; see Figure 3.


Figure 5. Configure the PLL for the AD9081. Figure 3. New PLL wizard


To simulate for fDAC = 12 Hz, simply change the DACCLK Freq green box to 12GHz, the CLKIN Freq is by default = 500MHz (see figure 6), then choose Next.


Figure 4. Select the loop filter design for the AD9081


Select the Loop Filter Design for complex chips containing PLLs; see Figure 4. Select the AD9081 from the Chip dropdown options,


then choose Next to configure the PLL synthesizer in the AD9081; see Figure 5. The graphical configuration page shows the block


diagram of the PLL and significant registers, frequencies and design options. On this page, you can choose from a range of standard configurations or alter registers and other options directly to configure the device. Here you can also directly input data to the boxes


surrounded in green, and the other cells update automatically. Counter values can be altered by hovering the cursor over the cell and using the mouse wheel. Options can be selected using dropdown lists. Frequency and register limits are checked in real time and errors are displayed in red, along with error messages; see Figure 6.


Figure 6. The PLL configured for the AD9081


Figure 7. The PLL reference selection www.electronicsworld.co.uk September 2024 25


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