Feature: Software & Tools
To use measured phase noise data of the Reference/CLKIN oscillator, you must place this data in a library file using the Reference Library Editor, you can then select this model From Library; see Figure 7. Refer to the ADIsimPLL Reference Model Creation section in this article for details on using this Editor. Click Next.
Figure 10. The ADIsimPLL components tab
By default, the reference phase noise is modelled as having a phase noise of None. To add reference noise, you can change the reference phase noise from None to Point/Floor (specify the phase noise at one point and the phase noise (PN) floor) as shown here, Corner/Floor (specify the phase noise floor and corner frequencies) or Leeson (specify oscillator parameters such as power, noise figure and loaded Q); see Figure 11.
Figure 8. The PLL setup
Choose the defaults for fast locking or low jitter and click Finish. Te Report tab (Figure 9) of the PLL synthesizer design prints
the frequency domain analysis at 12GHz and phase jitter using a brick wall filter. By selecting the tabs at the bottom of the screen, you can navigate directly to the Components, FreqDomain, Schematic, and DACn elements of the PLL synthesizer model.
Figure 11. Reference phase noise options
Te FreqDomain tab (Figure 12) displays the open loop gain and phase, and the output phase noise of the model. Te output phase noise represents the phase noise from the VCO measured when locked in the PLL. Tis includes contributions from all noise sources within the PLL. By expanding the FreqDomain folder in the data panel on the leſt, the min or max frequency of the plot can be changed as required.
Figure 9. The ADIsimPLL report tab
Te Components tab (Figure 10) allows you to check the VCO phase noise and reference phase noise at the analysis frequency (12GHz). Te VCO phase noise plot represents the phase noise from the VCO measured in a free running configuration (that is, unlocked - not in a PLL) at 12GHz. When the VCO is locked in a PLL the output phase noise is reduced significantly at frequencies inside the PLL loop bandwidth. Te reference\CLKIN phase noise represents the phase noise from the reference source. Te reference phase noise affects the output phase noise of the PLL, primarily inside the loop bandwidth.
26 September 2024
www.electronicsworld.co.uk
Figure 12. The ADIsimPLL FreqDomain tab
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