Column: Design with frequency components


the two. Whilst the pulling sensitivity is an intrinsic raw crystal property, the trimming sensitivity is an application- level measure describing how well the frequency can be fi ne-tuned in the oscillator circuit. T e pulling sensitivity C1


x 106 (C0+CL)2 /2 ppm/pF describes how much


the crystal’s oscillation frequency changes when the load capacitance changes. It depends on C1 C0


(shunt capacitance) and CL


(motional capacitance), (load


capacitance). T e trimming sensitivity is defi ned


as the frequency change (ppm) per unit change in trimming capacitor (pF) in the oscillator circuit. It includes the pulling sensitivity and the eff ect of the oscillator topology and capacitor arrangement. Figure 1 shows the dependency of the


pulling sensitivity with respect to the load capacitance at C0


= 2pF. It can be seen that for larger C1 . (larger


crystal blanks), the pulling sensitivity is higher; i.e. the crystal frequency moves more per pF change in CL Increasing CL


reduces how much frequency moves for the same trim error.


Hence, a design trade-off is: larger C1 (typical for larger packages) means easier to trim in-circuit but also more sensitive to layout and stray-capacitance changes; increasing CL


reduces sensitivity but can aff ect the oscillator start-up. Which means


that balancing a low ESR with the right CL whilst keeping a good pulling range for smaller package sizes is a challenge that the quartz manufactures have taken, being able to solve the technicalities of a wide range of applications. Still, for every demanding design


one needs to balance the technical requirements vs the space and power constraints.


Design verifi cation T e best way for an engineer to choose the right crystal for the design is to simulate its behaviour in an oscillator circuit using a simulation program like the GEYER Y-Quartz App. T is simulation process does not take long to check the accuracy of the design’s parameters in advance and save valuable design eff ort.


C1 CL L1


Figure 1: Pulling sensitivity vs load capacitance C0


= 2pF, S ≈ 0.5 C1 T e simulation allows modifi cations of


the crystal’s inherent parameters and the oscillator dimensioning until the oscillator circuit provides the optimum phase noise and gain, both a measure of the oscillator stability. A typical design using the app requires


the following input parameters: fL


R1 C0 – Nominal frequency of quartz crystal;


– ESR of quartz crystal (usually specifi ed as upper limit);


– Static capacitance of quartz crystal (usually specifi ed as upper limit);


– Dynamic (motional) capacitance of quartz crystal (rarely specifi ed);


– Nominal load capacitance of the quartz crystal;


– Dynamic inductance of the crystal (rarely specifi ed).


T ese values are specifi ed in the


component’s datasheet. Exact values can be found by analysing a batch of quartz crystals with a network analyser. Here is a simple application example to


illustrate the simulation. It is for a coff ee maker using a 2.0 x 1.6 mm 16MHz crystal. Coff ee machines work as standalone or


integrated in a smart home environment. In the simulation, the characteristics of a Pierce crystal oscillator can be optimised by inputting the corresponding values. You can visualise and vary the amplitude and phase characteristic of the feedback


/(C0


+ CL


)2


ppm/pF


circuit, consisting of the quartz crystal and surrounding components, for reliable oscillation without exceeding the maximal drive level of the crystal. T e simulation gives initial feedback


regarding the type of crystal that you need and the oscillator design performance. Once the component parameters have


been defi ned, the engineer usually requests samples from the crystal manufacturer and verifi es them on their evaluation board, performing the fi nal tuning of the oscillator part. Some manufacturers off er consulting, reference designs and prototyping support.


Bottom line With the right crystal choice and design discipline, precision and stability, trust in every clock cycle can be easily unlocked. T is consists of: • Selecting the right package size to balance compact design with long-term reliability;


• Ensuring the oscillator and crystal are matched for robust start-up and stable performance;


• Applying best practice PCB layout rules to safeguard frequency accuracy and low jitter;


• And last but not least: Aſt er the simulation, testing the timing design in real hardware.


T is series continues in the next edition of Electronics World


www.electronicsworld.co.uk November 2025 19


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