Column: Silicon systems design


principle. That principle includes open standards, data sharing and transparent validation methods. Collaboration between companies through shared verification IPs and measurable benchmarks can ensure composability without compromising quality or security. The Open Compute Project (OCP) has demonstrated what’s possible when companies collaborate through shared standards instead of guarding them. The OCP Chiplet Marketplace, for example, enables designers to mix and match verifi ed building blocks without starting from zero. As shown in Figure 3, the Open


into an adaptive, data-driven process by learning from historical regressions, recognising recurring failure patterns and predicting coverage gaps. While modularity enables fl exibility,


it also increases verifi cation complexity. Each chiplet brings its own protocols, timing behaviour and corner cases. To manage this growing scope, design teams are now applying AI-driven automation to tasks such as log analysis, regression triage, coverage closure prediction, failure pattern detection and intelligent test generation. Machine-learning tools are being


integrated into mainstream verifi cation workfl ows. T eir role is not to replace engineers but to extend visibility across millions of simulation cycles and large debug datasets. AI models trained on previous regression data can fl ag anomalies earlier, locate root causes faster and recommend potential fi xes whilst maintaining traceability. Such AI-driven capabilities allow verifi cation teams to move from reactive debugging to proactive quality improvement. As shown in Figure 2, AI engines


augment traditional verification workflows by automating feature extraction, test generation and constraint optimisation. Machine learning supports regression triage and coverage closure,


enabling faster, data-driven validation cycles.


Bridging hardware and software at scale The convergence of AI automation and hardware emulation is unlocking new efficiencies in system validation. The unique demands of AI hardware accelerators, characterised by massive parallelism, high computational workloads and stringent performance and power requirements, have elevated hardware-assisted verification (HAV) to a pivotal role in the design process. To address these challenges, hardware-


assisted solutions are increasingly coupled with machine-learning analytics to accelerate firmware validation, OS boot testing and application-level verification. By combining hardware acceleration


with AI-based insights, companies are improving verification throughput, design predictability and overall development efficiency. These advances are influencing mainstream verification strategies across global design teams.


Openness and collaboration as competitive advantage The emerging chiplet ecosystem will thrive only if openness becomes a shared


16 November 2025 www.electronicsworld.co.uk


Compute Project (OCP) integrates emerging IEEE standards to create a unifi ed framework for interoperable chiplet testing and verifi cation. T is model highlights how automation and open collaboration can streamline validation across diverse multi-die ecosystems. Complementing this, OCP’s Chiplet Test and System-in-Package (SiP) Verifi cation white papers defi ne open frameworks for testing and verifi cation across heterogeneous chiplet systems, reinforcing interoperability and accelerating industry adoption. We need that same collaborative energy for AI in verifi cation. Shared datasets, open benchmarks and transparent algorithms will make intelligent automation accessible to smaller design houses, not just the top tier. Today, design productivity defi nes


competitiveness across the industry. Openness and automation are essential to sustaining innovation and accelerating time to market. Focusing on transparency will accelerate innovation for the whole ecosystem, not just individual companies. Collaboration doesn’t just scale technology; it scales capability.


T is column continues in next month’s edition of Electronics World


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