Column: Silicon systems design


Figure 2: Example of an AI-enhanced verification flow


Open initiatives like the Universal


Chiplet Interconnect Express (UCIe) and the Open Compute Project (OCP) Universal D2D Link Layer are setting the foundation for multi-vendor interoperability. Tese standards define how dies communicate electrically and logically across heterogeneous packages. Tis shiſt is crucial for scaling integration without redesigning interconnect IP for every product. As major foundries, IP providers and


EDA vendors support these standards, the chiplet model is transitioning from proprietary projects to an established design practice.


AI as the new verification accelerator Te number of engineers, simulation runs or test benches no longer defines the semiconductor design lifecycle. It is increasingly defined by how intelligently teams can manage verification data. Traditional approaches struggle to maintain coverage closure, debug efficiency and turnaround time as designs scale to billions of transistors and trillions of simulation cycles. Tese challenges are precisely where artificial intelligence is reshaping verification. AI is turning verification from a reactive exercise


www.electronicsworld.co.uk November 2025 15 Figure 3: OCP’s vision for interoperable chiplet testing and verification


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